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is25lp080 d is25wp080 d is25wp040 d is25wp020 d 8/4/2mb serial flash memory with 133mhz multi i/ o spi & quad i/o qpi dtr interfac e data sheet
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 2 rev. a 09/02 /2016 features ? ind ustry standard serial interface - is25lp080 d : 8mbit/1mbyte - is25wp080 d : 8mbit/1mbyte - is25wp040 d : 4mbit/512kbyte (call factory) - is25wp020 d : 2mbit/256kbyte (call factory) - 256 bytes per programmable page - supports standard spi, fast, dual, dual i/o, quad, quad i/o, spi dtr, dual i/o dtr, quad i/o dtr, and qpi - supports serial flash discoverable parameters (sfdp) ? high performance serial flash (spi) - 50mhz normal and 133mhz fast read - 532 mhz equivalent qpi - dtr (dual transfer rate) up to 66mhz - selectable dummy cycles - configurable drive strength - supports spi modes 0 and 3 - more than 100,000 erase/program cycles - more than 20 - year data retention ? flexible & efficient memory architecture - chip erase with uniform: sector/blo c k era s e (4/32/64 k byte) - prog r am 1 to 256 by t es per page - program/erase s u s pend & re s ume ? efficient read and program modes - low instruction overhead operations - continuous read 8/16/32/64 - b y te burst wrap - selectable burst length - qpi for re d u c ed instru c tion overhe a d - autoboot operation ? low power with wide temp. ranges - single voltage supply is25lp: 2.30v to 3.60v is25wp: 1.65v to 1.95v - 10 ma active read current - 8 a standby current - 1 a deep power down - temp grades: extended: - 40c to +105c extended+: - 40c to +125c (call factory) auto grade: up to +125c note: extended+ should not be used for automotive. ? advanced security protection - software and hardware write protection - power supply lock protect - 4x256 - byte dedicated security area with otp user - lockable bits - 128 bit unique id for each device (call factory) ? industry standard pin - out & packages (1) - b = 8 - pin soic 208mil - n = 8 - pin soic 150mil - v = 8 - pin vvsop 150mil - k = 8 - contact wson 6x5mm - t = 8 - contact uson 4x3mm - u = 8 - contact uson 2x3mm - kgd (call factory) notes: 1 . call factory for other package options available 8/4/2mb s erial flash memory w ith 133mhz multi i/o spi & quad i/o qpi dtr int erface
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 3 rev. a 09/02 /2016 gen e r a l d e s c rip t i o n the is25lp080 d and is25wp080 d /040 d /020 d serial flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. issis indus try standard serial interface f lash is for systems that require limited space, a low pin count , and low power consumption . the device is accessed through a 4 - wire spi interface c onsisting of a serial data input ( si ), serial data output (so), serial clock (sck), and chip enable (ce#) pins, whi ch can also be configured to serve as multi - i/o (see pin descriptions). the device supports dual and quad i/o as well as standard , dual output, and quad o utput spi. clock frequencies of up to 133mhz allow for equivalent clock rates of up to 532mhz (133mhz x 4) which equates to 66mb ytes/s of data th roughput. the is25xp series of f lash adds support for dtr ( double transfer rate ) commands th at transfer address es and read data on both edges of the clock. these transfer rates can outperform 16 - bit parallel flash memories allowing for efficient memory access to support xip (execute in place) operation. the memory array is organized into program mable pages of 256 - bytes. this family supports page program mode whe re 1 to 256 bytes of data are programmed in a single command. qpi (quad periphe ral interface) supports 2 - cycle instruction further reducing instruction times. pages can be erased in groups of 4k b yte sectors, 32k b yte blocks, 64k b yte blocks, and/ or the entire chip. the uniform sector and block architecture allow s for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retent ion. glossary standard spi in this operation, a 4 - wire spi interface is utilized, consisting of serial data input (si), serial data output (so), serial clock (sck), and chip enable (ce#) pins. instructions are sent via the si pin to encode instructions, addresses, or input data to the device on the rising edge of sck. the so pin is used to read data or to check the status of the device. this device supports spi bus operation modes (0, 0) and (1, 1). multi i/o spi multi - i/o operation utilizes an enhanced spi protocol to allow the device to function with dual output, dual input and output, quad output, and quad input and output capability. executing these instructions through spi mode will achieve double or quadruple the transfer bandwidth for rea d and program operations. q pi the device supports quad peripheral interface (qpi) operations only when the device is switched from standard/dual/quad spi mode to qpi mode using the enter qpi (35h) instruction. the typical spi protocol requires that the by te - long instruction code being shifted into the device only via si pin in eight serial clocks. the qpi mode utilizes all four i/o pins to input the instruction code thus requiring only two serial clocks. this can significantly reduce the spi instruction ov erhead and improve system performance. only qpi mode or spi/dual/quad mode can be active at any given time. enter qpi (35h) and exit qpi (f5h) instructions are used to switch between these two mode s, regardless of the non - volati le quad enable (qe) bit stat us in the status register. power reset or software reset will return the device into the standard spi mode. si and so pins become bidirectional i/o0 and i/o1, and wp# and hold# pins become i/o2 and i/o3 respectively during qpi mode. dtr in addition to spi and qpi features, the device also supports spi dtr read. spi dtr allows high data throughput while running at lower clock frequencies. spi dtr read mode uses both rising and falling edges of the clock to drive output, resulting in reduci ng input and output cycles by half.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 4 rev. a 09/02 /2016 table of contents features ................................ ................................ ................................ ................................ ............................ 2 gen e r a l d e s c rip t i o n ................................ ................................ ................................ ................................ .... 3 table of contents ................................ ................................ ................................ ................................ ......... 4 1. pin configuration ................................ ................................ ................................ ................................ ... 7 2. pin descriptions ................................ ................................ ................................ ................................ ...... 8 3. block diagram ................................ ................................ ................................ ................................ .......... 9 4. spi modes description ................................ ................................ ................................ ........................ 10 5. system configuration ................................ ................................ ................................ ........................ 12 5.1 block/sector addresses ................................ ................................ ................................ ............ 12 6. registers ................................ ................................ ................................ ................................ ................. 13 6.1 status register ................................ ................................ ................................ .............................. 13 6.2 function register ................................ ................................ ................................ .......................... 16 6.3 re ad register and extended register ................................ ................................ .................. 17 6.4 autoboot register ................................ ................................ ................................ ........................ 21 7. protection mode ................................ ................................ ................................ ................................ ... 22 7.1 hardware write protection ................................ ................................ ................................ ...... 22 7.2 software write protection ................................ ................................ ................................ ...... 22 8. device operation ................................ ................................ ................................ ................................ .. 23 8.1 normal read operation (nord, 03 h ) ................................ ................................ ......................... 26 8.2 fast read operation (f rd, 0b h ) ................................ ................................ ................................ .. 28 8.3 hold operation ................................ ................................ ................................ ................................ 30 8.4 fast read dual i/o operation (frdio, bb h ) ................................ ................................ ............. 30 8.5 f a s t r e a d d u a l o u t p u t ope r a t i o n ( f rdo, 3b h ) ................................ ................................ ..... 33 8.6 f a s t r e a d quad o u t p u t ope r a t i o n ( f rqo, 6b h ) ................................ ................................ .... 34 8.7 fast read quad i/o operation (frqio, eb h ) ................................ ................................ ............ 36 8.8 page program operation (pp, 02 h ) ................................ ................................ ............................ 40 8.9 quad input page program operation (pp q , 32 h /38 h ) ................................ .......................... 42 8.10 erase operation ................................ ................................ ................................ ........................... 43 8.11 sector erase operation (ser, d7 h /20 h ) ................................ ................................ ................. 44 8.12 block erase operation (ber32k:52 h , ber64k:d8 h ) ................................ .............................. 45 8.13 chip erase operation (cer, c7 h /60 h ) ................................ ................................ ....................... 47 8.14 write enable operation (wren, 06 h ) ................................ ................................ ...................... 48 8.15 write disable operation (wrdi, 04 h ) ................................ ................................ ....................... 49 8.16 read status register operation (rdsr, 05 h ) ................................ ................................ ..... 50 8.17 write status register operati on (wrsr, 01 h ) ................................ ................................ ... 51 8.18 read function register operation (rd f r, 48 h ) ................................ ................................ . 52 8.19 write function register operation (wr f r, 42 h ) ................................ ............................... 53 8.20 enter quad peripheral interface (qpi) mode operat ion (qpien, 35 h ; qpidi, f5 h ) .. 54 8.21 program/erase suspend & resume ................................ ................................ ........................ 55
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 5 rev. a 09/02 /2016 8.22 enter deep power down (dp, b9 h ) ................................ ................................ ........................... 57 8.23 release deep power down (rdpd, ab h) ................................ ................................ ................. 58 8.24 set read parameters operation (srpnv: 65 h , srpv: c0 h /63 h ) ................................ ........ 59 8.25 set extended read parameters operation (serpnv: 85 h , serpv: 83 h ) ...................... 61 8.26 read read parameters operation (rdrp, 61 h ) ................................ ................................ ... 62 8.27 read extended read parameters operation (rderp, 81 h ) ................................ ............ 63 8.28 clear extended read parameters operation (clerp, 82 h ) ................................ .......... 64 8.29 read product identification (rdid, ab h ) ................................ ................................ .............. 65 8.30 read product identification by jedec id operation (rdjdid, 9f h ; rdjdidq, af h ) .. 67 8.31 read device manufacturer and device id operation (rdmdid, 90 h ) .......................... 68 8.31 read unique id number (rduid, 4b h ) ................................ ................................ ........................ 69 8.32 read sfdp operation ( rdsfdp, 5a h ) ................................ ................................ ........................ 70 8.33 no operation (nop, 00 h ) ................................ ................................ ................................ ............... 70 8.34 software reset (reset - enable (rsten , 66h ) and reset (rst , 99h )) and hardware reset ................................ ................................ ................................ ................................ .......................... 71 8.35 security information row ................................ ................................ ................................ ........ 72 8.36 information row erase operation ( irer, 64h) ................................ ................................ ... 73 8.37 information row program operation ( irp, 62h) ................................ ............................... 74 8.38 information row read operation ( irrd, 68h) ................................ ................................ ..... 75 8.39 fast read dtr mode operation in spi mode (f rdtr, 0d h ) ................................ ................ 76 8.40 fast read dual io dtr mode operation (f rddtr, bd h ) ................................ .................... 78 8.41 fast read quad io dtr mode operation in spi mode (frqdtr, ed h ) ............................ 81 8.42 sector lock/unlock functions ................................ ................................ .............................. 85 8.43 autoboot ................................ ................................ ................................ ................................ .......... 87 9. electrical characteristics ................................ ................................ ................................ ............. 91 9.1 absolute maximum ratings (1) ................................ ................................ ................................ ..... 91 9.2 operating range ................................ ................................ ................................ ............................. 91 9.3 dc characteristics ................................ ................................ ................................ ........................ 92 9.4 ac measurement conditions ................................ ................................ ................................ ...... 93 9.5 pin capacitance ................................ ................................ ................................ ............................... 93 9.6 ac c haracteristics ................................ ................................ ................................ ........................ 94 9.7 serial input/output timing ................................ ................................ ................................ .......... 96 9.8 power - up and power - down ................................ ................................ ................................ ........ 98 9.9 program/erase performance ................................ ................................ ................................ ... 99 9.10 reliability characteristics ................................ ................................ ................................ ..... 99 10. p ackage type information ................................ ................................ ................................ ......... 100 10.1 8 - pin jedec 208mil broad small outline integrated circuit (soic) package (b) ............................ 100 10.2 8 - pin jedec 150mil broad small outline integrated circuit (soic) package (n) ............................ 101 10.3 8 - pin 150mil vvsop package (v) ................................ ................................ ................................ ...... 102 10.4 8 - contact ultra - thin small outl ine no - lead (uson) package 2x3mm (u) ................................ ...... 103 10.5 8 - contact ultra - thin small outline no - lead (uson) package 4x3mm (t) ................................ ....... 104
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 6 rev. a 09/02 /2016 10.6 8 - contact ultra - thin small outline no - lead (wson) package 6x5mm (k) ................................ ...... 105 11. ordering information - valid part numbers ................................ ................................ ............... 106
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 7 rev. a 09/02 /2016 1. pin configuration 6 3 ce# vcc sck si (io0 ) 7 8 5 4 1 2 gnd wp# (io2) so (io1) hold # or reset# (io3) 8 - pin soic 208mil (package: b) 8 - pin soic 150mil (package: n) 8 - pin vvsop 150mil (package: v) 8 - pin uson 2x3mm (package: u ) 8 - pin uson 4x3mm (package: t) 8 - pin wson 6x5mm (package: k) hold # or reset# (io3) vcc ce# gnd sck 1 2 3 4 7 6 5 so (io1) si (io0 ) 8 wp# (io2) (1) (1)
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 8 rev. a 09/02 /2016 2. pin descriptions symbol type description ce# input chip enable: the chip enable (ce#) pin enables and disables the devices operation. when ce# is high the device is deselected and output pins are in a high impedance state. when deselected the devices non - critical internal circuitry power down to allow minimal levels o f power consumption while in a standby state. when ce# is pulled low the device will be selected and brought out of standby mode. the device is considered active and instructions can be written to, data read, and written to the device. after power - up, ce# must transition from high to low before a new instruction will be accepted. keeping ce# in a high state deselects the device and switches it into its low power state. data will not be accepted when ce# is high. si (io0), so (io1) input/output serial data input, serial output, and ios (si, so, io0, and io1): this device supports standard spi, dual spi, and quad spi operation. standard spi instructions use the unidirectional si (serial input) pin to write instructions, addresses, or data to the device on th e rising edge of the serial clock (sck). standard spi also uses the unidirectional so (serial output) to read data or status from the device on the falling edge of the serial clock (sck). in dual and quad spi mode, si and so become bidirectional io pins to write instructions, addresses or data to the device on the rising edge of the serial clock (sck) and read data or status from the device on the falling edge of sck. quad spi instructions use the wp# and hold# pins as io2 and io3 respectively. wp# (io 2 ) i nput/output write protect/serial data io (io2): the wp# pin protects the status register from being written in conjunction with the srwd bit. when the srwd is set to 1 and the wp# is pulled low, the status register bits (srwd, qe, bp3, bp2, bp1, bp0) are write - protected and vice - versa for wp# high. when the srwd is set to 0, the status register is not write - protected regardless of wp# state. when the qe bit is set to 1, the wp# pin (write protect) function is not available since this pin is used for i o2. hold# or reset# (io 3 ) input/output hold# or reset#/serial data io (io3): when the qe bit of status register is set to 1, hold# pin or reset# is not available since it becomes io3. when qe=0, the pin acts as hold# or reset# and either one can be selected by the p7 bit setting in read register. hold# will be selected if p7=0 (default) and reset# will be selected if p7=1 . the hold# pin allows the device to be paused while it is selected. it p auses serial communication by the master device without re setting the serial sequence. the hold# pin is active low. when hold# is in a low state and ce# is low, the so pin will be at high impedance. device operation can resume when hold# pin is brought to a high state. reset# pin is a hardware reset signal. when reset# is driven high, the memory is in the normal operating mode. when reset# is driven low, the memory enters reset mode and output is high - z. if reset# is driven low while an internal write, program, or erase operation is in progress, data may be lost. sck input serial data clock: synchronized clock for input and output timing operations. vcc power power: device core power supply gnd ground ground: connect to ground when referenced to vcc nc unused nc: pins labeled nc stand for no connect and should be left unconnected.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 9 rev. a 09/02 /2016 3. block diagram note1: according to the p7 bit setting in read register, either hold# (p7=0) or reset# (p7=1) pin can be selected. (1) si (io0) wp# (io 2 ) so (io 1 ) control logic high voltage generator i / o buffers and data latches 256 bytes page buffer y - decoder x - decoder serial peripheral interface status register address latch & counter memory array ce # sck wp # ( io 2 ) si ( io 0 ) so ( io 1 ) hold # or reset # ( io 3 )
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 10 rev. a 09/02 /2016 4. spi modes description multiple is25lp080 d device or multiple is25wp080 d /040 d /020 d devices can be connected on the spi serial bus and controlled by a spi master, i.e. micro controller, as shown in figure 4 . 1 . the devices support either of two spi modes: mode 0 (0, 0) mode 3 (1, 1) the difference between these two modes is the clock polarity . w hen the spi master is in s tand - by mode , the serial clock remains at 0 (sck = 0) for mode 0 and the clock remains at 1 (sck = 1) for mode 3. please refer to figure 4 .2 and figure 4 .3 for spi and qpi mode . in both modes, the input data is latched on the rising edge of serial clock (sck), and the output data is available from the falling edge of sck. figure 4 . 1 connection diagram among spi master and spi slaves (memory devices) notes: 1. according to the p7 bit setting in read register, either hold# (p7=0) or reset# (p7=1) pin can be selected. 2. si and so pins become bidirectional io0 and io1 respectively during dual i/o mode and si, so, wp#, and hold# pins become bidirectional io0, io1, io2, and io3 respectively during quad i/o or qpi mode. (1) (1) (1) spi interface with ( 0 , 0 ) or ( 1 , 1 ) spi master ( i . e . microcontroller ) spi memory device spi memory device spi memory device sck so si sck sdi sdo ce # wp # hold # or reset sck so si ce # wp # hold # or reset # sck so si ce # wp # cs 3 cs 2 cs 1 hold # or reset #
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 11 rev. a 09/02 /2016 figure 4 . 2 spi mode support figure 4 . 3 qpi mode support note1: msb (most significant bit) s c k s o s i m o d e 0 ( 0 , 0 ) m o d e 3 ( 1 , 1 ) m s b m s b s c k 20 ce # sck 4 0 4 0 3 - byte address 16 12 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 io 0 io 1 21 5 1 5 1 17 13 9 22 6 2 6 2 18 14 10 7 3 3 19 15 11 mode bits io 2 io 3 c 4 c 0 c 1 c 5 c 2 c 6 c 3 c 7 1 4 0 4 0 5 1 5 1 6 2 6 2 3 3 4 5 6 0 1 2 3 ... ... ... ... data 1 data 2 data 3 23 1 7 1 7 1 7 1 7 1 6
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 12 rev. a 09/02 /2016 5. system configuration the memory array is divided into uniform 4 k byte sectors or uniform 32/ 64 k byte blocks (a block consists of eight/ sixteen adjacent sectors respectively ). table 5. 1 illustrates the memory map of the device. the status register controls how the memory is protected . 5.1 block/sector address es table 5. 1 block/sector addresses note : 1. 4mb/2mb will be available only for 1.8v device. memory density block no. (64kbyte) block no. (32kbyte) sector no. sector size (kbytes) address range 2mb (1) 4mb (1) 8mb block 0 block 0 sector 0 4 000000h C 000fffh : : : block 1 : : : sector 15 4 00f000h - 00ffffh block 1 block 2 sector 16 4 010000h C 010fffh : : : block 3 : : : sector 31 4 01f000h - 01ffffh : : : : : block 3 block 6 sector 48 4 0 3 0000h C 0 3 0fffh : : : block 7 : : : sector 63 4 0 3 f000h C 0 3 ffffh : : : : : block 7 block 14 sector 112 4 070000h C 070fffh : : : block 15 : : : sector 127 4 07f000h C 07ffffh : : : : : block 15 block 30 sector 240 4 0f0000h C 0f0fffh : : : block 31 : : : sector 255 4 0ff000h C 0fffffh
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 13 rev. a 09/02 /2016 6. registers the device has four sets of registers: status, function, read, and autoboot . 6.1 status register status register format and status register bit definitions are described in table 6.1 & table 6.2. table 6.1 status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd qe bp3 bp2 bp1 bp0 wel wip d efault 0 0 0 0 0 0 0 0 table 6.2 status register bit definition bit name definition read - /write type bit 0 wip write in progress bit: "0" indicates the device is ready (default) "1" indicates a write cycle is in progress and the device is busy r volatile bit 1 wel write enable latch: "0" indicates the device is not write enabled (default) "1" indicates the device is write enabled r/w 1 volatile bit 2 bp0 b lock protection bit: (see table 6. 4 for details) "0" indicates the specific blocks are not write - protected (default) "1" indicates the specific blocks are write - protected r/w non - volatile bit 3 bp1 bit 4 bp2 bit 5 bp3 bit 6 qe quad enable bit: 0 indicates the quad output function disable (default) 1 indicates the quad output function enable r/w non - volatile bit 7 srwd status register write disable: (see table 7.1 for details) "0" indicates the status register is not write - protected (default) "1" indicates the status register is write - protected r/w non - volatile note 1 : wel bit can be written by wren and wrdi commands, bu t cannot by wrsr command. the bp0, bp1, bp2, bp3 , qe, and srwd are non - volatile memory cells that can be written by a write status register (wrsr) instruction. the default value of the bp0, bp1, bp2, bp3 , qe, and srwd bits were set to 0 at factory. the status register can be read by the read status register (rdsr). the function of status register bits are described as follows: wip bit : write in progress (wip) is read - only, and can be used to detect the progress or completion of a program, erase, or wri te/set non - volatile/otp register operation. wip is set to 1 (busy state) when the device is executing the operation. during this time the device will ignore further instructions except for read status/function/extended read register and software/hardware reset instructions. in addition to the instructions, an erase/program suspend instruction also can be executed during a program or an erase operation. when an operation has completed, wip is cleared to 0 (ready state) whether the operation is successful or not and the device is ready for further instructions. wel bit : write enable latch (wel) indicates the status of the internal write enable latch. when wel is 0, the internal write enable latch is disabled and the write operations described in table 6.3 are inhibited. when wel is 1, the w rite operations are allowed. wel bit is set by a write enable (wren) instruction. each w rite non - volatile r egister, p rogram and e rase instruction must be preceded by a wren instruction. the volat ile register related commands such as the set volatile read register and the set volatile extended read register dont require to set wel to 1". wel can be reset by a write disable (wrdi) instruction. it will automatically reset after the completion of an y w rite operation .
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 14 rev. a 09/02 /2016 table 6.3 instructions requiring w ren instruction ahead instruction s must be preceded by the wren instruction name hex code operation pp 02h serial input page program ppq 32h/38h quad input page program ser d7h/20h sector erase 4kb ber32 (32k b ) 52h block erase 32k b ber64 (64k b ) d8h block erase 64k b cer c7h/60h chip erase wrsr 01h write status register wrfr 42h write function register srpnv 65h set read parameters (non - volatile) serpnv 85h set extended read parameters (non - volatile) irer 64h erase information row irp 62h program information row wrabr 1 5h write autoboot register bp3, bp2, bp1, bp0 bits : the block protection ( bp3, bp2, bp1 and bp0) bits are used to define the portion of the memory area to be protected. refer to t able 6. 4 for the block w rite protection (bp) bit settings. when a defined combination of bp3, bp2, bp1 and bp0 bits are set, the corresponding memory area is protected. any program or erase operation to that area will be inhibited. note: a chip erase (c er) instruction will be ignored unless all the block protection bits are 0s. srwd bit : the status register write disable (srwd) bit operates in conjunction with the write protection (wp#) signal to provide a hardware protection mode. when the srwd is se t to 0, the status register is not write - protected. when the srwd is set to 1 and the wp# is pulled low (v il ), the bits of status register (srwd, qe, bp3, bp2, bp1, bp0) become read - only, and a wrsr instruction will be ignored. if the srwd is set to 1 and wp# is pulled high (v ih ), the status register can be changed by a wrsr instruction. qe bit : the quad enable (qe) is a non - volatile bit in the status register that allows q uad operation. when the qe bit is set to 0 , the pin wp# and hold#/reset# are enable d . when the qe bit is set to 1, the io2 and io3 pin s are enable d . warning: the qe bit must be set to 0 if wp# or hold#/reset# pin is tied directly to the power supply.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 15 rev. a 09/02 /2016 table 6.4 block (64kbyte) assignment by block write protect (bp) bits status register bits protected memory area bp3 bp2 bp1 bp0 8 mbit 4 mbit (1) 2 mbit (1) 0 0 0 0 none none none 0 0 0 1 1 block : 15 1 block : 7 1 block : 3 0 0 1 0 2 blocks : 14 - 15 2 blocks : 6 - 7 2 blocks : 2 - 3 0 0 1 1 4 blocks : 12 - 15 4 blocks : 4 - 7 all blocks 0 1 0 0 8 blocks : 8 - 15 all blocks 0 1 0 1 all blocks 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 8 blocks : 0 - 7 1 1 0 0 4 blocks : 0 - 3 4 blocks : 0 - 3 1 1 0 1 2 blocks : 0 - 1 2 blocks : 0 - 1 2 blocks : 0 - 1 1 1 1 0 1 block : 0 1 block : 0 1 block : 0 1 1 1 1 none none none note : 1. 4mb/2mb will be available only for 1.8v device.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 16 rev. a 09/02 /2016 6.2 function register function register format and bit definition are described in table 6. 5 and table 6. 6. table 6.5 function register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irl3 irl2 irl1 irl0 esus psus reserved reserved default 0 0 0 0 0 0 0 0 table 6.6 function register bit definition bit name definition read /write type bit 0 reserved reserved r reserved bit 1 reserved reserved r reserved bit 2 psus program suspend bit: 0 indicates program is not suspend 1 indicates program is suspend r volatile bit 3 esus erase suspend bit : "0" indicates erase is not suspend "1" indicates erase is suspend r volatile bit 4 ir lock 0 lock the information row 0: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w otp bit 5 ir lock 1 lock the information row 1: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w otp bit 6 ir lock 2 lock the information row 2: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w otp bit 7 ir lock 3 lock the information row 3: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w otp note: once otp bits of function register are written to 1, it cannot be modified to 0 any more. psus bit : the program suspend status bit indicates when a program operation has been suspended. the psus changes to 1 after a suspend command is issued during the p rogram operation. once the suspended program resumes, the psus bit is reset to 0 . esus bit : the erase suspend status bit indicates when an erase operation has been suspended. the esus bit is 1 after a suspend command is issued during an erase operation. once the suspended erase resumes, the esus bit is reset to 0 . ir l ock bit 0 ~ 3 : the de fault is 0 so that the information row can be programmed . if the bit set to 1, the information row can t be programmed. once it set to 1, it cannot be changed back to 0 s ince ir lock bits are otp.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 17 rev. a 09/02 /2016 6.3 read register and extended registe r read register format and bit definitions are described below. read register and extended read register consist of a pair of rewritable non - volatile register and vol atile register , respectively. during power up sequence, volatile register will be loaded with the value of non - volatile value. 6.3.1 read register table 6. 7 and table 6.8 define all bits that control features in spi/qpi modes. hold#/reset# pin selection (p7) bit is used to se lect hold# pin or reset# pin in spi mode when qe=0. when qe=1 or in qpi mode, p7 bit setting will be ignored since the pin becomes io3. . the dummy cycle bits (p6, p5, p4, p3) define how many dummy cycles are used during various read modes. the wrap sel ection bits (p2, p1, p0) define burst length with an enable bit. the set read parameters operation s (srpnv: 65h, srpv: c0h or 63h) are used to set all the read register bits, and can thereby define hold#/reset# pin selection, dummy cycles, and burst lengt h with wrap around. srpnv is used to set the non - volatile register and srpv is used to set the volatile register. table 6.7 read register parameter bit table p7 p6 p5 p4 p3 p2 p1 p0 hold# / reset# dummy cycles dummy cycles dummy cycles dummy cycles wrap enable burst length burst length default 0 0 0 0 0 0 0 0 table 6.8 read register bit definition bit name definition read - /write type p 0 burst length burst length r /w non - volatile and volatile p 1 burst length burst length r/w non - volatile and volatile p 2 burst length set enable burst length set enable bit: "0" indicates disable (default) "1" indicates enable r/w non - volatile and volatile p3 dummy cycles number of dummy cycles: bits1 to bit4 can be toggled to select the number of dummy cycles (1 to 15 cycles) r/w non - volatile and volatile p4 dummy cycles r/w non - volatile and volatile p5 dummy cycles r/w non - volatile and volatile p6 dummy cycles r/w non - volatile and volatile p7 hold# / reset# hold# / reset# pin selection bit: "0" indicates the hold# pin is selected (default) "1" indicates the reset# pin is selected r/w non - volatile and volatile table 6.9 burst length d ata p1 p0 8 bytes 0 0 16 bytes 0 1 32 bytes 1 0 64 bytes 1 1
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 18 rev. a 09/02 /2016 table 6.10 wrap function wrap around boundary p2 whole array regardless of p1 and p0 value 0 burst length set by p1 and p0 1 table 6.11 r e ad dummy cycles vs max frequency p[6:3 ] dummy cycles 2,3 fast r ead 5 0bh fast r ead 5 0bh fast read dual output 3bh fast read dual io bbh f ast read quad output 6bh fast read quad io ebh frdtr 0dh frddtr bdh frqdtr edh spi qpi spi spi spi spi, qpi spi/qpi spi 4 spi, qpi 0 default 1 133mhz 104mhz 133mhz 115mhz 133mhz 104mhz 66/66mhz 66mhz 66mhz 1 1 84mhz 33mhz 84mhz 60mhz 66 mhz 33mhz 50/20mhz 33mhz 20mhz 2 2 104mhz 50mhz 104mhz 84mhz 80mhz 50mhz 66/33mhz 50mhz 33mhz 3 3 133mhz 60mhz 115mhz 104mhz 90mhz 60mhz 66/46mhz 66mhz 46mhz 4 4 133mhz 70mhz 133mhz 115mhz 104mhz 70mhz 66/60mhz 66mhz 60mhz 5 5 133mhz 84mhz 133mhz 133mhz 115mhz 84mhz 66/66mhz 66mhz 66mhz 6 6 133mhz 104mhz 133mhz 133mhz 133mhz 104mhz 66/66mhz 66mhz 66mhz 7 7 133mhz 115mhz 133mhz 133mhz 133mhz 115mhz 66/66mhz 66mhz 66mhz 8 8 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66/66mhz 66mhz 66mhz 9 9 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66/66mhz 66mhz 66mhz 10 10 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66/66mhz 66mhz 66mhz 11 11 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66/66mhz 66mhz 66mhz 12 12 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66/66mhz 66mhz 66mhz 13 13 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66/66mhz 66mhz 66mhz 14 14 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66/66mhz 66mhz 66mhz 15 15 133mhz 133mhz 133mhz 133mhz 133mhz 133mhz 66/66mhz 66mhz 66mhz notes: 1. default dummy cycles are as follows. operation command dummy cycles comment normal mode dtr mode normal mode dtr mode fast read ( spi mode) 0bh 0dh 8 8 rduid , irrd instructions are also applied. fast read ( qpi mode) 0bh 0dh 6 6 fast read dual output 3bh - 8 - fast read dual io spi bbh bdh 4 4 fast read quad output 6bh - 8 - fast read quad io ( spi mode) ebh edh 6 6 fast read quad io ( qpi mode) ebh edh 6 6 2. enough number of dummy cycles must be applied to execute properly the ax read operation. 3. must satisfy bus i/o contention. for instance, i f the number of dummy cycles and ax bit cycles are same, then x must be hi - z. 4. qpi mode is not available for frddtr command . 5. rduid , irrd instructions are also applied.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 19 rev. a 09/02 /2016 6.3.2 extended read register table 6.1 2 and table 6.13 define all bits that control features in spi/qpi modes. the ods2, ods1, ods0 ( eb 7, eb 6, eb 5) bits provide a method to set and control driver strength. the four bits (eb3, eb2, eb1, eb0) are read - only bits and may be checked to know what the wip status is or whether there is an error during an erase, program, or write/set register operation. these bits are not affected by serpnv or serpv commands. eb4 bit remains reserved for future use. the set extended read parameters operation s ( serpnv: 85h, serpv: 83h ) are used to set all the extended read register bits, and can thereby define the output driver strength used during read modes. srpnv is used to set the non - volatile register and srpv is used to set the volatile register. table 6.12 extended read register bit table eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 ods2 ods1 ods0 reserved e_err p_err prot_e wip default 1 1 1 1 0 0 0 0 table 6.13 extended read register bit definition bit name definition read - /write type eb0 wip write in progress bit: has exactly same function as the bit0 (wip) of status register 0: ready, 1: busy r volatile eb1 prot_e protection error bit: "0" indicates no error "1" indicates protection error in an erase or a program operation r volatile eb2 p_err program error bit: "0" indicates no error "1" indicates an program operation failure or protection error r volatile eb 3 e_err erase error bit: "0" indicates no error "1" indicates a erase operation failure or protection error r volatile eb 4 reserved reserved r reserved eb 5 ods0 output driver strength: output drive strength can be selected according to table 6.14 r/w non - volatile and volatile eb 6 ods1 r/w non - volatile and volatile eb 7 ods2 r/w non - volatile and volatile table 6.14 driver strength table ods2 ods1 ods0 description remark 0 0 0 reserved 0 0 1 12.50% 0 1 0 25% 0 1 1 37.50% 1 0 0 reserved 1 0 1 75% 1 1 0 100% 1 1 1 50% default
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 20 rev. a 09/02 /2016 wip bit : the definition of the wip bit is exactly same as the one of status register. prot_e bit : the protection error bit indicates whether an erase or program operation has attempted to modify a protected array sector or block, or to access a locked information row region. when the bit is set to 1 it indicates that there was an error or errors in previous erase or program operations . see table 6.15 for details. p_err bit : the program error bit indicates whether a program operation has succeeded or failed, or whether a program operation has attempted to program a protected array sector/block or a locked information row region. when t he bit is set to 1 it indicates that there was an error or errors in previous program or write/set non - volatile register operations. see table 6.15 for details. e_err bit : the erase error bit indicates whether an erase operation has succeeded or failed, or whether an erase operation has attempted to erase a protected array sector/block or a locked information row region. when the bit is set to 1 it indicates that there was an error or errors in previous erase or write/set non - volatile register operatio ns. see table 6.15 for details. table 6.15 instructions to set prot_e, p_err, or e_err bit instructions description pp/ppq the commands will set the p_err if there is a failure in the operation. attempting to program within the protected array sector/block or within an erase suspended sector/block will result in a programming error with p_err and prot_e set to 1. irp the comman d will set the p_err if there is a failure in the operation. in attempting to program within a locked information row region , the operation will fail with p_err and prot_e set to 1. wrsr/wrabr/srpnv/ serpnv the update process for the non - volatile register bits involves an erase and a program operation on the non - volatile register bits. if either the erase or program portion of the update fails, the related error bit ( p_err or e_err) will be set to 1. only for wrsr command, when status register is write - protected by srwd bit and wp# pin, attempting to write the register will set prot_e and e_err to 1. wrfr the commands will set the p_err if there is a failure in the operation. ser/ber32k/ber64k/cer/ irer the commands will set the e_err if there is a failure in the operation. e_err and prot_e will be set to 1 when the user attempts to erase a protected main memory sector/block or a locked info rmation row region. chip erase (cer) command will set e_err and prot_e if any block protection bits (bp 3~bp0) are not 0. . notes : 1. otp bits in the function register may only be programmed to 1. writing of the bits back to 0 is ignored and no error is set. 2. read only bits in registers are never modified by a command so that the corresponding bits in the w rite /set register command data byte are ignored without setting any error indication. 3. once the prot_e, p_err, and e_err error bits are set to 1, they remains set to 1 until they are cleared to 0 with a clear extended read register (clerp) command. th is means that those error bits must be cleared through the clerp command. alternatively, hardware reset, or software reset may be used to clear the bits. 4. any further command will be executed even though the error bits are set to 1.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 21 rev. a 09/02 /2016 6.4 autoboot regist er auto b oot register bit ( 32 bits) definitions are described in table 6.1 5 . table 6.16 auto b oot register parameter bit table bits symbols function type default value description ab[31:24] absa reserved reserved 00h reserved for future use ab[23:5] absa autoboot start address non - volatile 00000h 3 2 byte boundary address for the start of boot code access ab[4:1] absd autoboot start delay non - volatile 0h number of initial delay cycles between ce # going low and the first bit of boot code being transferred , and it is the same as dummy cycles of frd (qe=0) or frqio (qe=1). example: the number of initial delay cycles is 8 ( qe=0) or 6 (qe=1) when ab[4:1] = 0h (default setting). ab0 abe autoboot enable non - volatile 0 1 = autoboot is enabled 0 = autoboot is not enabled
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 22 rev. a 09/02 /2016 7. protection mode the device supports hardware and software write - protection mecha nisms . 7.1 hardware write protection the write protection (wp#) pin provides a hardware write protection method for bp3, bp2, bp 1 , bp0 , srwd , and qe in the status register. refer to the section 6.1 status register. w rite inhibit voltage ( v wi ) is specified in the section 9. 8 power - up and power - down . a ll write sequence will be ignored when vcc drop s to v wi . table 7 .1 hardware write protection on status register srwd wp# status register 0 low writable 1 low protected 0 high writable 1 high writable note: before the execution of any program, erase or write status register instruction, the write enable latch (wel) bit must be enabled by executing a write enable (wren) instruction. if the wel bit is not enabled, the program, erase or write register instruction will be ignored. 7.2 software write prote ction the device also provi de s a sof tware write protection feature . the block protection ( bp3, bp2, bp1, bp0) bits allow part or the whole memory area to be write - protected.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 23 rev. a 09/02 /2016 8. device operation the device utilizes an 8 - bit instruction register. refer to table 8.1. instruction set for details on instructions and instruction codes. all instructions, addresses, and data are shifted in with the most significant bit (ms b ) first on serial data input (si) or seri al data ios (io0, io1, io2, io3). the input data on si or ios is latched on the rising edge of serial clock (sck) for normal mode and both of rising and falling edges for dtr mode after chip enable (ce#) is driven low (v il ). every instruction sequence star ts with a one - byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. ce# must be driven high (v ih ) after the last bit of the instruction sequence has been shifted in t o end the operation. table 8.1 instruction set instruction name operation mode byte0 byte1 byte2 byte3 byte4 byte5 byte6 nord normal read mode spi 03h a <23:16> a <15:8> a <7:0> data out frd fast read mode spi qpi 0bh a <23:16> a <15:8> a <7:0> dummy (1) byte data out frdio fast read dual i/o spi bbh a <23:16> dual a <15:8> dual a <7:0> dual axh (1),(2) dual dual data out frdo fast read dual output spi 3bh a <23:16> a <15:8> a <7:0> dummy (1) byte dual data out frqio fast read quad i/o spi qpi ebh a < 23:16> quad a <15:8> quad a <7:0> quad axh (1), (2) quad quad data out frqo fast read quad output spi 6bh a <23:16> a <15:8> a <7:0> dummy (1) byte quad data out frdtr fast read dtr mode spi qpi 0dh a <23:16> a <15:8> a <7:0> dummy (1) byte dual data out frddtr fast read dual i/o dtr spi bdh a <23:16> dual a <15:8> dual a <7:0> dual axh (1), (2) dual dual data out frqdtr fast read quad i/o dtr spi qpi edh a <23:16> a <15:8> a <7:0> axh (1), (2) quad quad data out pp input page program spi qpi 02h a <23:16> a <15:8> a <7:0> pd (256byte) ppq quad input page program spi 32h 38h a <23:16> a <15:8> a <7:0> quad pd (256byte) ser sector erase spi qpi d7h 20h a <23:16> a <15:8> a <7:0> ber32 (32kb) block erase 32k byte spi qpi 52h a < 23:16> a <15:8> a <7:0> ber64 (64kb) block erase 64k byte spi qpi d8h a <23:16> a <15:8> a <7:0> cer chip erase spi qpi c7h 60h wren write enable spi qpi 06h wrdi write disable spi qpi 04h rdsr read status register spi qpi 05h sr wrsr write status register spi qpi 01h wsr data
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 24 rev. a 09/02 /2016 instruction name operation mode byte0 byte1 byte2 byte3 byte4 byte5 byte6 rdfr read function register spi qpi 48h data out wrfr write function register spi qpi 42h wfr data qpi en enter qpi mode spi 35h qpi di exit qpi mode qpi f5h persus suspend during program/erase spi qpi 75h b0h perrsm resume program/erase spi qpi 7ah 30h dp deep power down spi qpi b9h rdid, rdpd read id / release power down spi qpi abh xxh (3) xxh (3) xxh (3) id7 - id0 srpnv set read parameters (non - volatile) spi qpi 65h data in srpv set read parameters (volatile) spi qpi c0h 63h data in serpnv set extended read parameters (non - volatile) spi qpi 85h data in serpv set extended read parameters (volatile) spi qpi 83h data in rdrp read read parameters ( volatile ) spi qpi 61h data out rderp read extended read parameters ( volatile ) spi qpi 81h data out clerp clear extended read register spi qpi 82h rdjdid read jedec id command spi qpi 9fh mf7 - mf0 id15 - id8 id7 - id0 rdmdid read manufacturer & device id spi qpi 90h xxh (3) xxh (3) 00h mf7 - mf0 id7 - id0 01h id7 - id0 mf7 - mf0 rdjdidq read jedec id qpi mode qpi afh mf7 - mf0 id15 - id8 id7 - id0 rduid read unique id spi qpi 4bh a (4) <23:16> a (4) <15:8> a (4) <7:0> dummy byte data out rdsfdp sfdp read spi qpi 5ah a <23:16> a <15:8> a <7:0> dummy byte data out nop no operation spi qpi 00h rsten software reset enable spi qpi 66h rst software reset spi qpi 99h
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 25 rev. a 09/02 /2016 instruction name operation mode byte0 byte1 byte2 byte3 byte4 byte5 byte6 irer erase information row spi qpi 64h a <23:16> a <15:8> a <7:0> irp program information row spi qpi 62h a <23:16> a <15:8> a <7:0> pd (256byte) irrd read information row spi qpi 68h a <23:16> a <15:8> a <7:0> dummy byte data out secun - lock sector unlock spi qpi 26h a < 23:16> a <15:8> a <7:0> seclock sector lock spi qpi 24h rdabr read autoboot register spi qpi 14h wrabr write autoboot register spi qpi 15h data in 1 data in 2 data in 3 data in 4 notes: 1. the number of dummy cycles depends on the value setting in the table 6. 1 1 read dummy cycles. 2. axh has to be counted as a part of dummy cycles. x means dont care. 3. xx means dont care. 4. a<23: 9 > are dont care and a<8:4> are always 0.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 26 rev. a 09/02 /2016 8.1 normal read operatio n (no rd, 03 h ) the normal read (nord) instruction is used to read memory contents at a maximum frequency of 50 mhz. the nord instruction code is transmitted via the si line, followed by three address bytes (a23 - a0) of the first memory location to be read. a total of 24 address bits a re shifted in , but only a vm s b ( valid most significant bit ) - a 0 are decoded. the remaining bits (a23 C a vm s b+1 ) are ignored . the first byte address ed can be at any memory location. upon completion, any data on the si will be ignored. refer to table 8. 2 for the related address key. the first byte data (d7 - d0) is shifted out on the so line, msb first. a single byte of data, or up to the whole memory array, can be read out in one normal read instruction. the address is automatically incremented by one a fter each byte of data is shifted out. the read operation can be terminated at any time by driving ce# high (vih) after the data comes out. when the highest address of the device is reached, the address counter will roll over to the 000000h address, allowi ng the entire memory to be read in one continuous read instruction. if the normal read instruction is issued while an erase, program or write operation is in process (wip=1) the instruction is ignored and will not have any effects on the current operation . table 8.2 address key address 8mb 4mb 2mb a vm s b C a 0 a19 - a0 (a23 - a20=x) a18 - a0 (a23 - a19=x) a17 - a0 (a23 - a18=x) note: x=dont care
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 27 rev. a 09/02 /2016 figure 8.1 normal read sequence 7 6 ce # sck si 5 3 2 so 4 1 0 data out 1 instruction = 03 h 23 ce # sck si 3 2 so 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mode 3 mode 0 ... 7 6 5 3 2 4 1 0 t v data out 2 ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 28 rev. a 09/02 /2016 8.2 fast read operation ( f r d , 0b h ) the fast read (frd) instruction is used to read memory data at up to a 1 33 mhz clock. the fast read instruction code is followed by three address bytes (a23 - a0) and dummy cycles ( configurable, default is 8 clocks), transmitted via the si line, with each bit latched - in during the rising edge of sck. then the first data byte from the address is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatically incremented by one after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the ent ire memory to be read with a single fast read instruction. the fast read instruction is terminated by driving ce# high (vih). if the fast read instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored without affecting the current cycl e . figure 8.2 fast read sequence note: dummy cycles depends on read parameter setting . detailed information in table 6.11 read dummy cycles. instruction = 0 bh 3 - byte address 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ... 7 6 ce # sck si 5 3 2 so 4 1 data out 23 ce # sck si 3 2 so 1 0 high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... mode 3 mode 0 t v dummy cycles 0 ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 29 rev. a 09/02 /2016 fast read operation in qpi mode (frd , 0bh) the fast read (frd ) instruction is used also in qpi mode to read memory data at up to a 1 33 mhz clock. the fast read instruction code (2 clocks) is followed by three address bytes (a23 - a0 6 clocks ) and dummy cycles (configurable, default is 6 cycles) , transmitted via the io3, io2, io1 and io0 lines, with each bit latched - in during the rising edge of sck. then the first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatically incremented by one after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the ent ire memory to be read with a single fast read instruction. the fast read instruction in qpi mode is terminated by driving ce# high (vih). if the fast read instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction i s ignored without affecting the current cycle. the fast read sequence in qpi mode is also applied to the commands in the following table 8.3. table 8.3 address key instruction name operation hex code frqio fast read quad i/o ebh rduid read unique id 4bh irrd read information row 68h figure 8.3 fast read sequence in qpi mode note: number of dummy cycles depends on read parameter setting . d etailed information in table 6.1 1 read dummy cycles. 0 bh ce # sck io [ 3 : 0 ] 6 dummy cycles 3 - byte address 0 1 2 3 4 5 6 7 8 9 ... 13 14 15 16 17 mode 3 mode 0 23 : 20 7 : 4 3 : 0 7 : 4 3 : 0 data 1 data 2 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0 ... t v ... instruction
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 30 rev. a 09/02 /2016 8.3 hold operation hold# is used in conjunction with ce# to select the device . when the device is selected and a serial sequence is underway, hold# can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, hold# is brought low while the sck signal is low. to resume serial communication, hold# is brought high while the sck signal is low (sck may still toggle duri ng hold). inputs to si will be ignored while so is in the high impedance state , during hold . note: hold is not supported in dtr mode or with qe=1 or when reset# is selected for the hold# or reset# pin . timing graph can be refere nced in ac parameters figur e 9.4 . 8.4 fast read dual i/o operation ( frdio, bb h ) the frdio allows the address bits to be input two bits at a time. this may allow for code to be executed directly from the spi in some applications. the frdio instruction code is followed by three address bytes (a23 C a0) and dummy cycles (configurable, default is 4 c lock s ) , transmitted via the io 1 and io0 lines, with each pair of bits latched - in during the rising edge of sck. the address msb is input on io1, the next bit on io0, and this shift pattern cont inues to alternat e between the two lines. depending on the usage of ax read operation mode, a mode byte may be located after address input. t he first data byte addressed is shifted out on the io1 and io0 lines, with each pair of bits shifted out at a maxi mum frequency f ct , during the falling edge of sck. the msb is output on io1, while simultaneously the second bit is output on io0. figure 8 . 4 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented by one after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frdio instruction. frdio instructio n is terminated by driving ce# high (v ih ). the device supports the ax read operation by applying mode bits during dummy period . mo de bits consist of 8 bits, such as m7 to m0. four cycles after address input are reserved for mode bits in frdio execution . m7 to m4 are important for enabling this mode. m3 to m0 become dont care for future use. when m[7:4]=1010(a h ), it enables the ax read operation and subsequent frdio execution skips command code. it saves cycles as described in figure 8. 5. when the code is different from a xh ( where x is dont care ) , the device exits the ax read operation . after finishing the read operation, device becomes ready to receive a new command. spi or qpi mode configuration retains the prior setting. mode bit must be applied during dummy cycles. number of dummy cycle s in table 6.1 1 includes number of mode bit cycles. if dummy cycle s are configured as 4 cycles, data output will start right after mode bit is applied. i f the frdio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not affect the current cycle .
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 31 rev. a 09/02 /2016 figure 8.4 fast read dual i/o sequence (with command decode cycles) notes: 1. if the mode bits=axh ( where x is dont care ), it can execute the ax read mode (without command) . when the mode bits are different from axh, the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6. 1 1 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bit cycles are same, then x should be hi - z. 7 5 3 7 5 1 3 1 data out 1 instruction = bb h 22 ce # sck 2 0 6 4 3 - byte address high impedance 20 18 ... 0 1 2 3 4 5 6 7 8 9 10 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 mode 3 mode 0 ... t v 23 3 1 7 5 21 19 ... io 0 io 1 3 1 2 0 6 4 2 6 4 0 2 0 4 dummy cycles 7 5 3 1 6 4 2 0 7 5 ... 6 4 ... ce # sck io 0 io 1 data out 2 data out 3 mode bits mode bits
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 32 rev. a 09/02 /2016 figure 8.5 fast read dual i/o ax read sequence (without command decode cycles) notes: 1. if the mode bits=axh ( where x is dont care ), it will keep executing the ax read mode (without command) . when the mode b its are different from axh , the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.1 1 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the nu mber of dummy cycles and ax bit cycles are same, then x should be hi - z. 22 ce # sck 2 0 3 - byte address 20 18 ... 0 1 2 3 ... 11 12 13 14 15 16 17 18 19 20 21 mode 3 mode 0 23 3 1 21 19 ... io 0 io 1 4 dummy cycles 6 7 6 4 7 5 2 0 3 1 data out 1 t v 6 4 7 5 2 0 3 1 4 5 mode bits ... ... data out 2 ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 33 rev. a 09/02 /2016 8.5 f a s t r e a d d u a l o u t p u t ope r a t i o n ( f rdo, 3b h ) t he f rdo i n s t r u c t i o n i s u s ed to r ead m e m o r y da t a o n two o utp u t p i ns ea c h at up t o a 1 33 mhz c l o c k . t he f rdo i n s t r u c t i o n c o d e i s f o ll o wed b y th r e e add r e s s b y tes ( a 23 C a 0) a nd du m m y cycles (configurable, default is 8 clocks) , t r an s m i tted v i a t h e io0 l i n e, w i th ea c h b i t l at c h e d - i n du ri ng t he r i s i ng edge of s c k . t hen t h e f i rs t data b y t e a dd r e ss ed is s h i ft ed o ut o n t h e io 1 and io 0 li n e s , w i th e a c h p a i r of b i ts s h i f ted o u t at a m a x i m u m f r equen c y f c t , du ri ng t he f a l li n g e dge of s c k . t he f i rs t b i t ( msb ) i s ou t put on io 1 . s i m u l ta n eou s l y , the s e c ond b i t i s ou t put on io 0 . t he f i rs t b y t e a dd r e ss ed c a n be at an y m e m o r y l o c a t i on. t he add r e s s i s au t o m at i c a l l y i n cr e m ented by one a f ter ea c h b y te of data i s s h i f ted o ut. w hen the h i g he s t add r e s s i s r ea c h ed, the a d d r e s s c ounter w i l l r o l l o v er t o the 0 00 0 00h a d d r e ss , a l l o w i ng the en t i r e m e m o r y t o be r ead w i th a s i n g l e f rdo instruction. the frdo instruction is terminated b y d ri v i ng c e # h i gh ( vih ) . if the f rdo i n s t r u c t i on i s i ss ued wh i l e an e r a s e, p r og r am o r w r i te c y cl e i s i n p r o c e s s ( b u s y =1) the i n s t r u c t i on i s i gno r ed and w il l not ha v e any ef f e c ts on the c u rr ent c y cl e. figure 8.6 fast read dual output sequence note: dummy cycles depends on read parameter setting . detailed information in table 6.11 read dummy cycles. ce # sck 7 5 data out 1 instruction = 3 bh 23 ce # sck 3 2 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mode 3 mode 0 ... t v io 0 io 1 6 4 3 1 7 5 2 0 6 4 3 1 ... 2 0 ... data out 2 io 0 io 1 8 dummy cycles
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 34 rev. a 09/02 /2016 8.6 f a s t r e a d quad o u t p u t ope r a t i o n ( f rqo, 6b h ) the frqo instruction is used to read memory data on four output pins each at up to a 133 mhz clock. the frqo instruction code is followed by three address bytes (a23 C a0) and dummy cycles (configurable, default is 8 clocks) , transmitted via the io0 line, with each bit latched - in during the rising edge of sck. then the first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum frequency fct, during the falling edge of sck. the fi rst bit (msb) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqo instruction. frqo instruction is termin ated by driving ce# high (vih). if a frqo instruction is i ssued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 35 rev. a 09/02 /2016 figure 8.7 fast read quad output sequence note: dummy cycles depends on read parameter setting . detailed information in table 6.11 read dummy cycles. ce # sck 5 1 data out 1 instruction = 6 bh 23 ce # sck 3 2 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mode 3 mode 0 ... t v io 0 io 1 4 0 5 1 5 1 4 0 4 0 5 1 ... 4 0 ... io 0 io 1 8 dummy cycles high impedance io 2 high impedance io 3 7 3 6 2 7 3 7 3 6 2 6 2 7 3 ... 6 2 ... io 2 io 3 data out 2 data out 3 data out 4
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 36 rev. a 09/02 /2016 8.7 fast read quad i/o o peration ( frqio, eb h ) the frqio instruction allows the address bits to be input four bits at a time. this may allow for code to be executed directly from the spi in some applications. the frqio instruction code is followed by three address bytes (a23 C a0) and dummy cycles (configurable, default is 6 clocks ) , transmitted via the io3, io2, io 1 and io 0 lines, with each group of four bits latched - in during the rising edge o f sck. the address of msb input s on io3, the next bit on io2, the next bit on io1, the next bit on io0, and continue to shift in alternating on the four. depending on the usage of ax read operation mode, a mode byte may be located after address input. t he first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit ( msb ) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. figure 8 . 8 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest addre ss is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqio instruction. frqio instruction is terminated by driving ce# high (v ih ). the device supports the ax read operation by applyi ng mode bits during dummy period. mode bits consist of 8 bits, such as m7 to m0. two cycles after address input are reserved for mode bits in frqio execution. m7 to m4 are important for enabling this mode. m3 to m0 become dont care for future use. when m[ 7:4]=1010(ah), it enables the ax read operation and subsequent frqio execution skips command code. it saves cycles as described in figure 8. 9 . when the code is different from axh ( where x is dont care ), the device exits the ax read operation. after finishing the read operation, device becomes ready to receive a new command. spi or qpi mode configuration retains the prior setting. mode bit must be applied during dummy cycles. number of dummy cycle s in table 6.1 1 includes number of mode bit cy cles. if dummy cycles are configured as 6 cycles, data output will start right after mode bit s and 4 additional dummy cycles are applied . if the frqio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle .
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 37 rev. a 09/02 /2016 figure 8.8 fast read quad i/o sequence (with command decode cycles) notes: 1. if the mode bits=axh ( where x is dont care ), it can execute the ax read mode (without command) . when the mode bits are different from axh, the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.1 1 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bit cycles are same, then x should be hi - z. ce # sck 5 1 data out 1 instruction = ebh 20 ce # sck 4 0 4 0 3 - byte address high impedance 16 12 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mode 3 mode 0 ... t v io 0 io 1 4 0 5 1 5 1 4 0 4 0 5 1 4 0 io 0 io 1 21 5 1 5 1 17 13 9 22 6 2 6 2 18 14 10 23 7 3 7 3 19 15 11 mode bits io 2 io 3 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 data out 2 data out 3 data out 4 io 2 io 3 1 0 5 1 ... 4 0 ... 2 6 2 ... 3 7 3 ... 5 4 6 7 6 dummy cycles data out 5 data out 6
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 38 rev. a 09/02 /2016 figure 8.9 fast read quad i/o ax read sequence (without command decode cycles) notes: 1. if the mode bits=axh ( where x is dont care ), it will keep executing the ax read mode (without command) . when the mode bits are different from axh, the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.1 1 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bit cycles are same , then x should be hi - z. 20 ce # sck 4 0 4 0 3 - byte address 16 12 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 io 0 io 1 21 5 1 5 1 17 13 9 22 6 2 6 2 18 14 10 23 7 3 7 3 19 15 11 mode bits io 2 io 3 5 1 4 0 5 1 4 0 6 2 6 2 7 3 7 3 ... ... ... ... data out 1 data out 2 ... t v 6 dummy cycles
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 39 rev. a 09/02 /2016 fast read quad i/o operation in qpi mode (frqio , ebh) the frqio instruction is also used in qpi mode to read memory data at up to a 1 33 mhz clock. the frqio instruction in qpi mode utilizes all four io lines to input the instruction code so that only two clocks are required, while the frqio instruction in spi mode requires that the byte - long instruction code is shifted into the device only via io0 line in eight clocks. as a result, 6 command cycles will be reduced by the frqio instruction in qpi mode . in addition, subsequent address and data out are shifted in/out via all four io lines like the frqio instruction. in fact, except for the command cycle, the frqio operation in qpi mode i s exactly same as the frqio operation in spi mode . the device supports the ax read operation by applying mode bits during dummy period. mode bits consist of 8 bits, such as m7 to m0. two cycles after address input are reserved for mode bits in frqio execution. m7 to m4 are important for enabling this mode. m3 to m0 become dont care for future use. when m[7:4]=1010(ah), it enables the ax read operation and subsequent frqio execution skips command code. it saves cycles as described in figure 8.9 . when the code is different from axh (where x is dont care), t he device exits the ax read operation. after finishing the read operation, device becomes ready to receive a new command. spi or qpi mode configuration retains the prior setting. mode bit must be applied during dummy cycles. number of dummy cycles in table 6.11 includes number of mode bit cycles. if dummy cycles are configured as 6 cycles, data output will start right after mode bits and 4 additional dummy cycles are applied. if the frqio instruction is issued while an erase, program or write cycle is in p rocess (wip=1) the instruction is ignored and will not have any effects on the current cycle. figure 8.10 fast read quad i/o sequence in qpi mode note: number of dummy cycles depends on read parameter setting . detailed information in table 6.11 read dummy cycles. e bh ce # sck io [ 3 : 0 ] 6 dummy cycles 3 - byte address 0 1 2 3 4 5 6 7 8 9 ... 13 14 15 16 17 mode 3 mode 0 23 : 20 7 : 4 3 : 0 7 : 4 3 : 0 data 1 data 2 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0 ... t v instruction mode bits 7 : 4 3 : 0 ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 40 rev. a 09/02 /2016 8.8 pa ge program operation ( pp, 02 h ) the page program ( pp ) instruction allows up to 256 bytes data to be programmed into memory in a single operation. the destination of the memory to be programmed must be outside the protected memory area set by the block protection ( bp3, bp2, bp1, bp0) bits. a pp instruction which attempts to program into a page that is write - protected will be ignored. before the execution of pp instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the pp instruction code, three address bytes and program data (1 to 256 bytes) are input via the sl line. program operation will start immediately after t he ce# is brought high, otherwise the pp instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the p rogress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. the starting byte can be anywhere within the pag e. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation ca n alter 1s into 0 s. the same byte location or page may be programmed more than once, to incrementally change 1 s to 0 s. an erase operation is required to change 0 s to 1 s.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 41 rev. a 09/02 /2016 figure 8.11 page program sequence in spi mode figure 8.12 page program sequence in qpi mode instruction = 0 2 h 23 ce # sck si 7 6 so 7 3 - byte address high impedance 22 ... 0 data in 1 data in 256 0 1 ... 7 8 9 ... 31 32 33 ... 39 ... 207 2 ... 20 79 mode 3 mode 0 ... 0 ... ... 0 02 h ce # sck io [ 3 : 0 ] 3 - byte address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 23 : 20 7 : 4 3 : 0 7 : 4 3 : 0 data in 1 data in 2 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0 7 : 4 3 : 0 7 : 4 3 : 0 data in 3 data in 4 ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 42 rev. a 09/02 /2016 8.9 quad input page prog ram operation ( pp q , 32 h / 38 h ) the quad input page program instruction allows up to 256 bytes data to be programmed into memory in a single operation with four pins (io0, io1, io2 and io3) . the destination of the memory to be programmed must be outside the protected memory area set by the block protection ( bp3, bp2, bp1, bp0) bits. a quad input page program instruction which attempts to program into a page that is write - protected will be ignored. before the execution of quad input page program instruction, the qe bit in the status register must be set to 1 and the write enable latch (wel) must be enabled through a write enable (wren) instruction. the quad input page program instruction code, three address bytes and program data (1 to 256 bytes) are input via the four pins (io0, io1, io2 and io3). program operation will start immediately after the ce# is brought high, otherwise the quad input page prog ram instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent t o a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation can alter 1s into 0 s. the sam e byte location or page may be programmed more than once, to incrementally change 1 s to 0 s. an erase operation is required to change 0 s to 1 s. figure 8.13 quad input page program sequence instruction = 32 h / 38 h 23 ce # sck 4 0 4 0 3 - byte address high impedance 22 ... 0 0 1 2 3 4 5 6 7 8 9 31 32 33 34 35 mode 3 mode 0 io 0 io 1 5 1 5 1 6 2 6 2 7 3 7 3 data in 2 io 2 io 3 ... data in 1 ... ... ... ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 43 rev. a 09/02 /2016 8.10 erase operation the erase command sets all bits in the addressed sector or block to 1s. the memory array of the device is organized into uniform 4 k b yte sectors or 32/ 64 k b yte uniform blocks (a block consists of eight/ sixteen adjacent sectors respectively ). before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to 1). in order to erase the device, there are three erase instructions available: sector erase ( ser ), block erase ( ber) and chip erase (c er). a sector erase oper ation allows any individual sector to be erased without affecting the data in other sectors. a block erase operation erases any individual block. a chip erase operation erases the whole memory arr ay of a device. a sector erase, block erase , or chip erase o peration can be executed prior to any programming operation.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 44 rev. a 09/02 /2016 8.11 sector erase operati on (ser, d7 h /20 h ) a sector erase (ser) instruction erases a 4 k b yte sector before the execution of a ser instruction, the write enable latch (wel) must be set via a write e nable (wren) instruction. the wel bit is automatically reset after the completion of sector erase operation. a se r instruction is entered, after ce# is pulled low to select the device and stays low during the entire instruction sequence the se r instruction code, and three address bytes are input via si. erase operation will start immediately after ce# is pulled high. the internal control logic automatically handle s the erase voltage and timing. during an erase operation, all instruction will be ignored except the read status register (rdsr) instruction. the progress or completion of the erase operation can be determined by reading the wip bit in the status register using a rdsr instructi on. if the wip bit is 1, the erase operation is still in progress. if the wip bit is 0, the erase operation has been completed. figure 8.14 sector erase sequence in qpi mode figure 8.15 sector erase sequence in qpi mode instruction = d 7 h / 20 h 23 ce # sck si 3 2 so 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0 d 7 h / 20 h ce # sck io [ 3 : 0 ] 3 - byte address 0 1 2 3 4 5 6 7 mode 3 mode 0 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 45 rev. a 09/02 /2016 8.12 block erase operatio n (ber32k: 52 h , ber64k: d8 h ) a block erase (ber) instruction erases a 32/ 64k byte block. before the execution of a ber instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after the completion of a block erase opera tion. the ber instruction code and three address bytes are input via si. erase operation will start immediately after the ce# is pulled high, otherwise the ber instruction will not be executed. the internal control logic automatically handles the erase vo l tage and timing. figure 8.16 block erase (64 k ) sequence in spi mode figure 8.17 block erase (64 k ) sequence in qpi mode instruction = d 8 h 23 ce # sck si 3 2 so 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0 d 8 h ce # sck io [ 3 : 0 ] 3 - byte address 0 1 2 3 4 5 6 7 mode 3 mode 0 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 46 rev. a 09/02 /2016 figure 8.18 block erase (32k) sequence in spi mode figure 8.19 block erase (32k) sequence in qpi mode instruction = 52 h 23 ce # sck si 3 2 so 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0 52 h ce # sck io [ 3 : 0 ] 3 - byte address 0 1 2 3 4 5 6 7 mode 3 mode 0 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 47 rev. a 09/02 /2016 8.13 chip erase operation (cer, c7 h /60 h ) a chip erase (c er ) instruction erases the entire memory array. before the execution of c er instruction, the write enable latch (wel) must be set via a write enable ( wren) instruction. the wel is automatically reset after completion of a chip erase operation. the c er instruction code is input via the si. erase operation will start immediately after ce# is pulled high, otherwise the cer instruction will not be executed. the internal control logic automatically handle s the erase voltage and timing. chip erase (cer) ins truction can be executed only when block protection (bp3~bp0) bits are set to 0s. if the bp bits are not 0, the cer command is not executed and e_err and prot_e are set. figure 8.20 chip erase sequence in spi mode figure 8.21 chip erase sequence in qpi mode instruction = c 7 h / 60 h ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance c 7 h / 60 h ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 48 rev. a 09/02 /2016 8.14 write enable operati on ( wren, 06 h ) the write enable (wren) instruction is used to set the write enable latch (wel) bit. the wel bit is reset to the write - protected state after power - up. the wel bit must be write enabled before any write operation, including sector erase, block erase, chip erase, page program, program information row, write status register, write function register, set non - volatile read register, set non - volatile extended read register, and w rite autoboot register operations except for set volatile read register and set volatile extended read register. the wel bit will be reset to the write - protect ed state automatically upon completion of a write operation. the wren instruction is required bef ore any above operation is executed. figure 8.22 write enable sequence in spi mode figure 8.23 write enable sequence in qpi mode instruction = 06 h ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance 0 6 h ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 49 rev. a 09/02 /2016 8.15 write disable operat ion ( wrdi, 04 h ) the write disable (wrdi) instruction resets the wel bit and disables all write instructions. the wrdi instruction is not required after the execution of a write instruction, since the wel bit is autom atically reset. figure 8.24 write disable sequence in spi mode figure 8.25 write disable sequence in qpi mode instruction = 04 h ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance 0 4 h ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 50 rev. a 09/02 /2016 8.16 read status register operation ( rdsr, 05 h ) the read status register (rdsr) instruction provides access to the status register. during the execution of a program, erase or write status register operation, all other instructions will be ignored except the rdsr instruction, which can be used to check the progress or completion of an operation by reading the wip bit of status register. figure 8.26 read status register sequence in spi mode figure 8.27 read status register sequence in qpi mode instruction = 05 h 7 ce # sck si 3 2 so 1 0 data out 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 t v 05 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] t v data out
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 51 rev. a 09/02 /2016 8.17 write status registe r operation ( wrsr, 01 h ) the write status register (wrsr) instruction allows the user to enable or disable the block protection and status register write protection features by writing 0s or 1s into the non - volatile bp3, bp2, bp1, bp0 , and srwd bits. also wrsr instruction allows the user to disable or enable quad operation by writing 0 or 1 into the non - volatile qe bit. figure 8.28 write status register sequence in spi mode figure 8.29 write status register sequence in qpi mode instruction = 01 h ce # sck si so data in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 7 3 2 1 0 6 5 4 high impedence 01 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] data in
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 52 rev. a 09/02 /2016 8.18 read function register operation ( rd f r, 48 h ) the read function register (rd f r) instruction provides access to the function register . refer to table 6.6 function register bit definition for more detail. figure 8.30 read function register sequence in spi mode figure 8.31 read function register sequence in qpi mode instruction = 48 h 7 ce # sck si 3 2 so 1 0 data out 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 t v 48 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] t v data out
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 53 rev. a 09/02 /2016 8.19 write function register operation ( wr f r, 42 h ) information row lock bits (irl3~irl0) can be set to 1 individually by wrfr instruction in order to lock information row. since irl bits are otp, once it is set to 1, it cannot set back to 0 again. figure 8.32 write function register sequence in spi mode figure 8.33 write function register qpi sequence in qpi mode instruction = 42 h ce # sck si so data in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 7 3 2 1 0 6 5 4 high impedence 42 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] data in
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 54 rev. a 09/02 /2016 8.20 enter quad periphera l interface (qpi) mo de operation ( q pi en, 35 h ; qpi di, f5 h ) the enter quad peripheral interface (qpien) instruction, 35h, enables the flash device for qpi bus operation. upon completion of the instruction, all instructions thereafter will be 4 - bit multiplexed input/output until a power cycle or an exit quad p eripheral interface instruction is sent to device . the exit quad peripheral interface (qpidi) instruction, f5 h , resets the device to 1 - bit spi protocol operation. to execute an exit quad peripheral interface operation, the host drives ce# low, sends the q pidi instruction, then drives ce# high. the device just accepts qpi (2 clocks) command cycles. figure 8.34 enter quad peripheral interface (qpi) mode sequence figure 8.35 exit quad peripheral interface (qpi) mode sequence instruction = 35 h ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance f 5 h ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 55 rev. a 09/02 /2016 8.21 program/erase suspen d & resume the device al lows the interruption of sector erase, block erase , or page program operations to conduct other operations. 75h/b0h command for suspend and 7ah/30h for resume will be used. (spi/qpi all acceptable) function register bit2 (psus) and bit3 (esus) are used to check whether or not the device is in suspend mode. suspend to read ready timing: 10 0s resume to another suspend timing: 40 0s program/erase suspen d during sector - erase or block - e rase (persus 75h/ b0h) the program/erase suspend allows the interruption of sector erase and block erase operations. after the program/erase suspend, program, read related, resume and reset commands can be accepted. it is possible to nest a program/erase suspend operation during a program inside a program/erase suspend operation . refer to table 8.4 for more detail . to execute the program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle ( 75h/b0h ), then drives ce# high. the function r egister indicates that the erase has been suspended by changing the esus bit from 0 to 1 , but the device will not accept another command until it is ready. to determine when the device will accept a new command, p oll the wip bit in the status register or wait the specified time t su s . when esus bit is issued, the write enable latch (wel) bit will be reset. program/erase suspen d during page progra mming (persus 75h/ b0h) the program/erase suspend allows the interruption of a ll array program operations. after the program/erase suspend command, wel bit will be disabled, therefore only read related, resume and reset command can be accepted . refer to table 8. 4 for more detail . to execute the program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle ( 75h/b0h ), then drives ce# high. the function r egister indicates that the programming has been suspended by changing the psus bit from 0 to 1 , but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status register or wait the specified time t su s . program/erase resume (perrsm 7a h / 30h) the program/erase resume restarts the program or erase command that was suspended, and changes the suspend status bit in the function register (esus or psus bits) back to 0 . to execute the program/erase resume operation, the host drives ce# low, sends the program/erase resume command cycle ( 7ah/30h ), then drives ce# high. a cycle is two nibbles long, most significant nibble first. to determine if the internal, self - timed write operation com pleted, poll the wip bit in the status r egister, or wait the specified time t se , t be or t pp for sector erase, block erase, or page programming, respectively. the total write time before suspend and after resume will not exceed the uninterrupted write times t se , t be or t pp .
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 56 rev. a 09/02 /2016 table 8.4 instructions accepted during suspend operation suspended instruction allowed name hex code operation program or erase no rd 03h read data bytes from memory at normal read mode program or erase fr d 0bh read data bytes from memory at fast read mode program or erase frdio bbh fast read dual i/o program or erase frdo 3bh fast read dual output program or erase frqio ebh fast read quad i/o program or erase frqo 6bh fast read quad output program or erase frdtr 0dh fast read dtr mode program or erase frddtr bdh fast read dual i/o dtr program or erase frqdtr edh fast read quad i/o dtr erase pp 02h serial input page program erase ppq 32h/38h quad input page program erase wren 06h write enable program or erase rdsr 05h read status register program or erase rdfr 48h read function register program or erase clerp 82h clear extended read register program or erase perrsm 7ah/30h resume program/erase erase persus 75h/b0h program/erase suspend program or erase rdid abh read manufacturer and product id program or erase srpv c0/63h set read parameters (volatile) program or erase serpv 83h set extended read parameters (volatile) program or erase rdrp 61h read read parameters (volatile) program or erase rderp 81h read extended read parameters (volatile) program or erase rdjdid 9fh read manufacturer and product id by jedec id command program or erase rdmdid 90h read manufacturer and device id program or erase rdjdidq afh read jedec id qpi mode program or erase rduid 4bh read unique id number program or erase rdsfdp 5ah sfdp read program or erase nop 00h no operation program or erase rsten 66h software reset enable program or erase rst 99h reset (only along with 66h) program or erase irrd 68h read information row erase secunlock 26h sector unlock erase seclock 24h sector lock program or erase rdabr 14h read autoboot register
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 57 rev. a 09/02 /2016 8.22 enter deep power down (dp, b9 h ) the deep power - down (dp) instruction is for setting the device on the minimizing the power consumption (enter into power - d own mode) . during this mode, standby current is reduced from i sb1 to i sb2 . while in the power - down mode, the device is not active and all write/program/erase instructions are ignored. the instruction is initiated by driving the ce# pin low and shifting the instruction code into the device . the ce# pin must be driven high after the instruction has been latched , or power - down mode will not en gage . once ce# pin driven high, the p ower - down mode will be entered within the time duration of t dp . while in the p ower - down mode only the release from power - down/rdid instruction, which restores the device to normal operation, will be recognized. all othe r instructions are ignored , including the read status register instruction which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. it is availa ble in both spi and qpi mode. figure 8.36 enter deep power down mode sequence in spi mode figure 8.37 enter deep power down mode sequence in qpi mode instruction = b 9 h ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 t dp so high impedance b 9 h ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0 t dp
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 58 rev. a 09/02 /2016 8.23 release deep power d own (rdpd, ab h ) the release deep power - down/r ead device id instruction is a multi - purpose command . to release the device from the p ower - down m ode, the instruction is issued by driving the ce# pin low, shifting the instruction code ab h and driving ce# high . releas ing the device from p ower - down mode will take the time duration of t res1 before normal operation is restored and other instructions are accepted. the ce# pin must remain high during the t res1 time duration. if the release deep power - down/rdid instruction is issued while an era se, program or write cycle is in pro gr ess (wip = 1) the instruction is ignored and will not have any effects on the current cycle. figure 8.38 release deep power down mode sequence in spi mode figure 8.39 release deep power down mode sequence in qpi mode t res 1 instruction = abh ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance t res 1 abh ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 59 rev. a 09/02 /2016 8.24 set read parameters operation (srp nv : 65 h , srpv: c0 h / 63 h ) set read parameter bits this device supports configurable burst length and dummy cycles in both spi and qpi mode by setting three bits (p2, p1, p0) and four bits ( p6, p5, p4, p3 ) within the read register , respectively . to set those bits the srpnv and srpv operation instruction are used. details regarding burst length and dummy cycles can be found in t able 6. 9 , t able 6. 10 , and t able 6.1 1 . hold#/ reset# pin selection (p7) bit in the read register can be set with the srpnv and srpv operation as well, in order to select reset# pin instead of hold# pin. srpnv is used to set the non - volatile read register , while srpv is us ed to set the volatile read register. note: when srpnv is executed, the volatile read register is set as well as the non - volatile read register. figure 8.40 set read parameters sequence in spi mode figure 8.41 set read parameters sequence in qpi mode instruction = 65 h or c 0 h / 6 3 h ce # sck si so data in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 7 3 2 1 0 6 5 4 high impedence 65 h or c 0 h / 63 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] data in
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 60 rev. a 09/02 /2016 read with 8/16/32/64 - byte wrap around the device is capable of burst read with wrap around in both spi and qpi mode. the size of burst length is configurable by using p0, p1, and p2 bits in read register . p2 bit (wrap enable) enables the burst mode feature. p0 and p1 define the size of burst. burst lengths of 8, 16, 32 , and 64 bytes are supported. by default, address increases by one up through the entire array. by setting the burst length, the data being acce ssed can be limited to the length of burst boundary within a 256 byte page. the first output will be the data at the initial address which is specified in the instruction. following data will come out from the next address within the burst boundary. once t he address reaches the end of boundary, it will automatically move to the first address of the boundary. ce # high will terminate the command. for example, if burst length of 8 and initial address being applied is 0h, following byte output will be from add ress 00h and continue to 01h,..,07h, 00h, 01h until ce # terminate s the operation. if burst length of 8 and initial address being applied is feh(254 d ), following byte output will be from address feh and continue to ffh, f8h, f9h, fah, fbh, fch, fdh , and repeat from feh until ce # terminate s the operation. the command s , srpv (65h) or srpnv (c0h or 63h) , are used to configure the b urst length. if the following data input is one of 00h,01h,02h, and 03h, the device will be in default operation mode. it will be continuous burst read of the whole array. if the following data input is one of 04h,05h,06h, and 07h, the device will set the burst length as 8,16,32 and 64 , respectively. to exit the burst mode , another c0 h or 63h command is necessary to set p2 to 0. otherwise, the burst mode will be retained until either power down or reset operation. to change burst length , another c0 h or 63h command should be executed to set p0 and p1 (detailed information in table 6. 9 burst length dat a). all read commands will operate in burst mode once the read register is set to enable burst mode . refer to figure 8. 40 and figure 8. 4 1 for instruction sequence.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 61 rev. a 09/02 /2016 8.25 set extended read parameters oper ation (s e rp nv : 85 h , serpv: 83 h ) set read operational driver strength this device supports configura ble operational driver strength in both spi and qpi mode s by setting three bits (ods0, ods1, ods 2 ) within the e xtended read register . to set the ods bits the s e rp nv and serpv operation instruction s are required. the devices driver strength can be reduced as low as 12.50% of full drive strength. details regarding the d river strength can be found in t able 6.1 4 . serpnv is used to set the non - volatile extended read register, while serpv is used to set the volatile extended read register. notes: 1. the default driver strength is set to 50%. 2. when serpnv is executed, the volatile read extended register is set as well as the non - volatile read extended register. figure 8.42 set extended read parameters sequence in spi mode figure 8.43 s et extended read parameters sequence in qpi mode instruction = 8 5 h / 83 h ce # sck si so data in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 7 3 2 1 0 6 5 4 high impedence 8 5 h / 8 3 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] data in
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 62 rev. a 09/02 /2016 8.26 read read parameters oper ation ( rd rp, 61 h ) prior to, or a fter setting read register , the data of the read register can be confirmed by the rdrp command . the instruction is only applicable for the volatile r ead r egister, not for the non - volatile r ead r egister. figure 8.44 read read parameters sequence in spi mode figure 8.45 read read parameters sequence in qpi mode instruction = 61 h 7 ce # sck si 3 2 so 1 0 data out 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 t v 61 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] t v data out
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 63 rev. a 09/02 /2016 8.27 read extended read p arameters operation (rd e rp, 81 h ) prior to, or after setting e xtended read register , the data of the e xtended read register can be confirmed by the rd e rp command . the instruction is only applicable for the volatile e xtended read register , not for the non - volatile extended read register . during the execution of a program, erase or write non - volatile register operation, the rderp instruction will be executed, which can be used to check the progress or completion of an operation by reading the wip bit. figure 8.46 read extended read parameters sequence in spi mode figure 8.47 read extended read parameters sequence in qpi mode instruction = 81 h 7 ce # sck si 3 2 so 1 0 data out 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 t v 81 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] t v data out
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 64 rev. a 09/02 /2016 8.28 clear extended read parameters operation (clerp, 82 h ) a clear extended read register (clerp) instruction clears prot_e, p_err, and e_err error bits in the extended read register to 0 when the error bits are set to 1. once the error bits are set to 1, they remains set to 1 until they are cleared to 0 with a clerp command. figure 8.48 clear extended read parameters sequence in spi mode figure 8.49 clear extended read parameters sequence in qpi mode instruction = 82 h ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance 82 h ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 65 rev. a 09/02 /2016 8.29 read product identif ication (rdid, ab h ) the release from power - down /r ead device id instruction is a multi - purpose instruction. it can support bot h spi and qpi mode s . the read product identification (rdid) instruction is for reading out the old style of 8 - bit electronic signature, whose values are shown as table of product identification . the rdid instruction code is followed by three dummy bytes, each bit being latche d - in on si during the rising sck edge . then the device id is shifted out on so with the msb first, each bit been shifted out during the falling edge of sck. the rdid instruction is ended by driving ce# high. the device id ( id 7 - id0 ) outputs repeatedly if ad ditional clock cycles are continuously sent to sck while ce# is at low. table 8.5 product identification manufacturer id (mf7 - mf0) issi serial flash 9dh instruction abh 90h 9fh part number device id (id7 - id0) memory type + capacity (id15 - id0) is25lp080 d 13h 6014h is25wp080 d 13h 7014h is25wp040 d 12h 7013h is25wp020 d 11h 7012h figure 8.50 rdid ( read product identification ) sequence in spi m ode device id ( id 7 - id 0 ) data out 32 33 ... 39 instruction = ab h ce # sck si so 0 1 ... 7 8 9 ... 31 mode 3 mode 0 3 dummy bytes t v
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 66 rev. a 09/02 /2016 figure 8.51 rdid ( read product identification ) sequence in qpi m ode abh ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0 2 3 4 5 6 7 8 9 6 dummy cy c les device id ( id 7 - id 0 ) t v
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 67 rev. a 09/02 /2016 8.30 read pro duct identification by jedec id operation (rdjdid, 9f h ; rdjdidq, af h ) the jedec id read instruction allows the user to read the manufacturer and product id of devices. refer to table 8 . 5 product identification for manufacturer id and device id. aft er the jedec id r ead command (9fh in spi mode, afh in qpi mode) is input, the manufacturer id is shifted out msb first followed by the 2 - byte electronic id (id15 - id0) that indicates memory type and capacity , one bit at a time. each bit is shifted out during the falling edge of sck. if ce# stays low after the last bit of the 2 - b yte electronic id, the manufacturer id and 2 - byte electronic id will loop until ce# is pulled high. figure 8.52 rdjdid (read jedec id in spi m ode) sequence figure 8.53 rd jd idq ( read jedec id i n qpi mode ) sequence instruction = 9 fh memory type ( id 15 - id 8 ) ce # sck si capacity ( id 7 - id 0 ) so 0 1 ... 7 8 9 ... 15 16 17 ... 23 24 25 ... 31 mode 3 mode 0 manufacturer id ( mf 7 - mf 0 ) t v afh ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 4 5 7 : 4 3 : 0 6 7 7 : 4 3 : 0 mf 7 - mf 0 id 15 - id 8 id 7 - id 0 t v
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 68 rev. a 09/02 /2016 8.31 read de vice manufacturer an d device id operation (rdmdid, 90 h ) the read device manufacturer and device id (rdmdid) instruction allows the user to read the m anufacturer and product id of devices. refer to table 8 . 5 product identification for m anufacturer id and d evice id. the rdmdid instruction code is followed by two dummy bytes and one byte address (a7~a0), each bit being latched - in on si during the rising e dge of sck. if one byte address is initially set as a0 = 0, then the m anufacturer id is shifted out on so with the msb first followed by the d evice id ( id 7 - id0 ) . each bit is shifted out during the falling edge of sck. if one byte address is initially set as a0 = 1, then d evice id will be read first followed by the m anufacture r id . the m anufacture r and d ev ice id can be read continuously alternating between the two until ce# is driven high. figure 8.54 rdmdid ( read product identification ) sequence in spi m ode note s : 1. address a0 = 0, will output the 1 - byte manufacture r id (mf7 - mf0) ? 1 - byte d evice id (id7 - id0) address a0 = 1, will outpu t the 1 - byte d evice id (id7 - id0) ? 1 - byte manufacture r id (mf7 - mf0) 2. the manufacture r and device id can be read continuously and will alternate from one to the other until ce# pin is pulled high. figure 8.55 rdmdid ( read product identification ) sequence in qpi m ode notes : 1. address a0 = 0, will output the 1 - byte manufacturer id (mf7 - mf0) ? 1 - byte device id (id7 - id0) address a0 = 1, will output the 1 - byte device id (id7 - id0) ? 1 - byte manufacturer id (mf7 - mf0) 2. the manufacturer and device id can be read continuously and will alt ernate from one to the other until ce# pin is pulled high. instruction = 90 h manufacturer id ( mf 7 - mf 0 ) ce # sck si device id ( id 7 - id 0 ) so 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 - b yte address t v 90 h ce # sck io [ 3 : 0 ] 3 - byte address 0 1 2 3 4 5 6 7 8 9 10 11 mode 3 mode 0 23 : 20 7 : 4 3 : 0 7 : 4 3 : 0 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0 t v instruction manufacturer id ( mf 7 - mf 0 ) device id ( id 7 - id 0 )
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 69 rev. a 09/02 /2016 8.31 read unique id numbe r (rduid, 4b h ) the read unique id number (rduid) instruction accesses a factory - set read - only 16 - byte number that is unique to the device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the rduid instruction is instated by driving the ce# pin low and shifting the instruction code (4bh) followed by 3 address bytes and dummy cycles (configurable, default is 8 clocks). after which, the 16 - byte id is shifted out on the falling edge of sck as shown below. as a result, t he sequence of rduid instruction is same as fast read. rduid qpi sequence is also same as fast read qpi except for the instruction code. refer to the fast read qpi operation. note: 16 byte s of data will repeat as long as ce# is low and sck is toggling. figure 8.56 rduid sequence note: dummy cycles depends on read parameter setting . detailed information in table 6.11 read dummy cycles. table 8.6 unique id addressing a[23:16] a[15:9] a[8:4] a[3:0] xxh xxh 00h 0h byte address xxh xxh 00h 1h byte address xxh xxh 00h 2h byte address xxh xxh 00h xxh xxh 00h fh byte address note: xx means dont care. instruction = 4 bh dummy cycles ce # sck si so 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 byte address data out t v ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 70 rev. a 09/02 /2016 8.32 read sfdp operation ( rdsfdp, 5a h ) the serial flash discoverable parameters (sfdp) standard provides a consistent method of describing the functions and features of serial flash devices in a standard set of internal parameter tables. these parameters can be inte rrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. for more details please refer to the jedec standard jesd 216 (serial flash discoverable parameters). the sequence of issuing rdsfdp instr uction in spi mode is : ce# goes low ? send rdsfdp instruction (5ah) ? send 3 address bytes on si pin ? 8 dummy cycles on si pin ? read sfdp code on so ? end rdsfdp operation by driving ce# high at any time during data out. refer to issis application note for sfdp table. the data at the addresses that are not specified in sfdp table are undefined. rdsfdp sequence in qpi mode, has 8 dummy cycles before sfdp code, too. figure 8.57 rdsfdp ( read sfdp ) sequence in spi mode 8.33 no operation (nop , 00 h ) the no operation command solely cancels a reset enable command and has no impact on any other command s . it is available in both spi and qpi mode s . to execute a nop, the host drives ce# low, sends the nop command cycle (00h), then drives ce# high. instruction = 5 ah dummy cycles ce # sck si so 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 byte address data out t v ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 71 rev. a 09/02 /2016 8.34 s oftware r eset (r eset - e nable (rsten , 66 h ) and reset (rst , 99 h )) and hardware reset the software reset operation is used as a system reset that puts the device in normal operating mode. during the reset operation, the value of volatile registers will default back to the value in the corresponding non - volatile register. this operation consists of two commands: reset - enable (rsten) and reset (rst). the operation requires the reset - enable command followed by the reset command. any command other than the reset command after the reset - enable command will disable the reset - enable. execute the ce# p in low ? sends the reset - enable command (66 h ), and drives ce# high. next, the host drives ce# low again, sends the reset command (99 h ), and pulls c e # high. only if the reset# pin is enabled, hardware reset function is available. for all other packages except the package with dedicated reset# pin (or ball) option, the reset# pin (or ball) will be solely applicable in spi mode and when the qe bit is disabled. for the package with dedicated reset# pin (or ball) , the reset# pin (or ball) is always applicable regardless of the qe bit value in status register and hold#/reset# selection bit (p7) in read register. the dedicated reset# pin has an internal pull - up resistor and may be left floating if not used. the reset# pin (or ball) has the highest priority among all the input signals and will reset the device to its initial power - on state regardless of the state of all other pins (ce#, ios, sck, and wp#) . in order to activate hardware reset, the reset# pin (or ball) must be driven low for a minimum period of t reset (1 s). drive reset# low for a minimum period of t reset will interrupt any on - going internal and external operations , release the device from deep power down mode 1 , disable all input signals, force the output pin enter a s tate of high impedance, and reset all the read parameters. if the reset# pulse is driven for a period shorter than 1s, it may still reset the device, however the 1s minimum period is recommended to ensure the reliable operation. the required wait time after activating a hw reset before the device will accept another instruction (t hwrst ) is the same as the maximum value of t sus (100s). the software/hardware reset during an active program or erase operation aborts the operation, which can result in corr upting or losing the data of the targeted address range. depending on the prior operation, the reset timing may vary. recovery from a write operation will require more latency than recovery from other operations. note1: the status and function registers re main unaffected. figure 8.58 s oftware reset enable and software r eset sequence in spi mode ( rsten, 66h + rst, 99h ) instruction = 66 h ce # sck si 0 1 mode 3 mode 0 2 3 4 5 6 7 instruction = 99 h 8 9 10 11 12 13 14 15 so high impedance
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 72 rev. a 09/02 /2016 figure 8.59 software reset enable and software reset sequence in qpi mode ( rsten, 66h + rst, 99h ) 8.35 security information row the security information row is comprised of an additional 4 x 256 bytes of programmable information . the security bits can be reprogrammed by the user. any program security instruction issued while an erase, program or write cycle is in progress is rejected without having any effect on the cycle that is in progress. table 8.7 information row valid address range address assignment a [23:16] a [15:8] a[7:0] irl0 (information r ow l ock0) 00h 00h byte address irl1 00h 10h byte address irl2 00h 20h byte address irl3 00h 30h byte address bit 7~4 of the function register is used to permanently lock the programmable memory array. when function register bit irlx = 0 , the 256 bytes of the programmable memory array can be programmed. when function register bit irlx = 1 , the 256 bytes of the programmable memory array function as read only . 66 h ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0 99 h 0 1
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 73 rev. a 09/02 /2016 8.36 information row eras e operation ( irer, 64 h ) information row erase (irer) instruction erases the data in the information row x (x : 0~3) array . prior to the operation, t he write enable latch (wel) must be set via a write enable (wren) instruction. the wel bit is automatically reset after the completion of the operation. the sequence of i r er operation: pull ce# low to select the device ? send irer instruction code ? send three address bytes ? pull ce# high. ce# should remain low during the entire instruction sequence. once ce# is pulled high, erase operation will begin immediately. the internal control logic automatically handle s the erase voltage a nd timing. figure 8.60 i r er ( information row erase ) sequence instruction = 64 h 23 ce # sck si 3 2 so 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 74 rev. a 09/02 /2016 8.37 information row prog ram operation ( irp, 62 h ) the information row program ( ir p ) instruction allows up to 256 bytes data to be programmed into the memory in a single operation. before the execution of irp instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the i r p instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input . three address bytes has to be input as specified in the table 8. 7 information row valid address range . program operation will sta rt once the ce# goes high, otherwise the i r p instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instructio n. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page . t he previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation can alter 1s into 0s, the same byte location or information row array may be programmed more tha n once to incrementally change 1 to 0s. a n erase operation is required to change 0s back to 1s. figure 8.61 irp ( information row program ) sequence instruction = 6 2 h 23 ce # sck si 7 6 so 7 3 - byte address high impedance 22 ... 0 data in 1 data in 256 0 1 ... 7 8 9 ... 31 32 33 ... 39 ... 207 2 ... 20 79 mode 3 mode 0 ... 0 ... ... 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 75 rev. a 09/02 /2016 8.38 information row read operation ( irrd, 68 h ) the i rrd instruction is used to read memory data at up to a 1 33 mhz clock. the irrd instruction code is followed by three address bytes (a23 - a0) and dummy cycles (configurable, default is 8 clocks) , transmitted via the si line, with each bit latched - in during the rising edge of sck. then the first data byte addressed is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the address is automatically incremented by one after each byte of data is shif ted out. once the address reaches the last address of each 256 byte information row, the next address will not be valid and the data of the address will be garbage data. it is recommended to repeat four times irrd operation that reads 256 byte with a valid starting address of each information row in order to read all data in the 4 x 256 byte information row array. the irrd instruction is terminated by driving ce# high (vih). if a n irrd instruction is issued while an erase, program or write cycle is in pro cess (wip=1) the instruction is ignored and will not have any effects on the current cycle . t he sequence of irrd instruction is same as fast read except for the instruction code. irrd qpi sequence is also same as fast read qpi except for the instruction code. refer to the fast read qpi operation. figure 8.62 irrd ( information row read ) sequence note: dummy cycles depends on read parameter setting . detailed information in table 6.11 read dummy cycles. instruction = 68 h dummy cycles ce # sck si so 0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47 mode 3 mode 0 3 byte address data out t v ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 76 rev. a 09/02 /2016 8.39 fast read dtr mode operation in spi mode (f rdtr, 0d h ) the frdtr instruction is for doubling the data in and out . s ignals are triggered on both rising and falling edge of clock. the address is latched on both rising and falling edge of sck, and data of each bit shifts out on both risin g and falling edge of sck at a maximu m frequency f c 2 . the 2 - bit address can be latched - in at one clock, and 2 - bit data can be read out at one clock, which means one bit at the rising edge of clock, the other bit at the falling edge of clock. the first add ress byte can be at any location. the address is automatically increased to the next higher address after each byte of data is shifted out, so the whole memory can be read out in a single frdtr instruction. the address counter rolls over to 0 when the high est address is reached. the sequence of issuing frdtr instruction is: ce# goes low ? s ending frdtr instruction code (1bit per clock) ? 3 - byte address on si (2 - bit per clock) ? 8 dummy clocks (configurable , default is 8 clocks ) on si ? d ata out on so (2 - bit per clock) ? e nd frdtr operation via driving ce# hi gh at any time during data out. while a program/erase/write status register cycle is in progress, frdtr instruction will be rejected without any effect on the current cycle. figure 8.63 frdtr sequence in spi mode note: dummy cycles depends on read parameter setting . detailed information in table 6.11 read dummy cycles. ce # sck si so data out 1 instruction = 0 dh ce # sck si so 3 - byte address high impedance 0 1 2 3 4 5 6 7 8 9 10 ... 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ... mode 3 mode 0 t v 23 22 21 0 7 6 5 4 3 2 1 0 data out 2 7 6 5 4 3 2 1 0 data out ... 7 6 8 dummy cy c les 20 19 18 17 5 ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 77 rev. a 09/02 /2016 fast read dtr mode operation in qpi mode (frdtr, 0dh) the frdtr qpi instruction utilizes all four io lines to input the instruction code so that only two clocks are required, while the frdtr instruction requires that the byte - long instruction code is shifted into the device only via io0 line in eight clocks. in addition, subsequent address and data out are shifted in/out via all four io lines unlike the frdtr instruction. eventually this operation is same as the frq dtr qpi , but the only different thing is that ax mode is not available in the frdtr qpi operatio n. the sequence of issuing frdtr qpi instruction is: ce# goes low ? sending frdtr qpi instruction ( 4 - bit per clock) ? 24 - bit address interleave on io 3, io 2, io 1 & io 0 (8 - bit per clock) ? 6 dummy clocks (configurable , default is 6 clocks ) ? data out interleave on io 3, io 2, io 1 & io 0 (8 - bit per clock) ? end frdtr qpi operation by driving ce# high at any time during data out. if the fr dtr qpi instruction is issued while a program/erase/write status register cycle is in progress (wip=1), the i nstruction will be rejected without any effect on the current cycle. figure 8.64 frdtr sequence in qpi mode notes: 1. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 2. sufficient dummy cycles are required to avoid i/o contention. instruction = 0 dh ce # sck 3 - byte address 0 1 2 3 4 5 6 7 8 9 10 11 12 mode 3 mode 0 t v 20 16 12 5 1 21 17 13 4 0 io 0 io 1 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 6 dummy cycles io 2 io 3 6 2 7 3 5 1 4 0 6 2 7 3 data out data out ... 4 0 5 1 6 2 7 3 ... ... ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 78 rev. a 09/02 /2016 8.40 fast read d ual io dtr mode operation (f rddtr, bd h ) the frddtr instruction enables double transfer rate throughput on dual i/o of the device in read mode. the ad dress (interleave on dual i/o pins) is latched on both rising and falling edge of sck, and the data (interleave on dual i/o pins) shift out on both rising and falling edge o f sck at a maximum frequency f t2 . the 4 - bit address can be latched - in at one clock, and 4 - bit data can be read out at one clock, w hich means two bits at the rising edge of clock, the other two bits at the falling edge of clock. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte of data is shifted out, so the whole memory can be read out with a single frddtr instruction. the address counter rolls over to 0 when the highest ad dress is reached. once writing frddtr instructio n, the following address/dummy/ data out will perform as 4 - bit instead of previous 1 - bit. the sequence of issuing frddtr instruction is: ce# goes low ? s ending frddtr instruction (1 - bit per clock) ? 24 - bit address interleave on io 1 & io 0 (4 - bit per clock) ? 4 dummy clocks (configurable , default is 4 clocks ) on io 1 & io 0 ? d ata out inter leave on io 1 & io 0 (4 - bit per clock) ? e nd frddtr operation via pulling ce# high at any time during data out (please refer to figure 8 . 6 4 for 2 x i/o double transfer rate read mode timing waveform). if axh ( where x is dont care ) is input for the mode bits during dummy cycles, the device will enter ax read operation mode which enables subsequent frddtr execution skips command code. it saves cycles as described in figure 8. 6 5 . when the code is different from axh , the device exits the ax read operation. after finishing the read operation, device becomes ready to receive a new command. if the frddtr instruction is issued w hile a program/erase/write status register cycle is in progress (wip=1) , the instruction will be rejected withou t any effect on the current cycle.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 79 rev. a 09/02 /2016 figure 8.65 frddtr sequence (with command decode cycles) notes: 1. if the mode bits=axh ( where x is dont care ), it can execute the ax read mode (without command) . when the mode bits are different from axh, the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.1 1 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bit cycles are same, then x should be hi - z. ce # sck io 0 io 1 instruction = bdh ce # sck io 0 io 1 3 - byte address high impedance 0 1 2 3 4 5 6 7 8 9 10 ... 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 mode 3 mode 0 ... t v 22 20 18 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 4 dummy cy c les 23 21 19 1 data out ... 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 data out data out data out data out data out 16 14 12 17 15 13 10 11 7 5 6 4 3 1 2 0 mode bits ... mode bits ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 80 rev. a 09/02 /2016 figure 8.66 frddtr ax read sequence (without command decode cycles) notes: 1. if the mode bits=axh ( where x is dont care ), it will keep executing the ax read mode (without command) . when the mo de bits are different from axh , the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.1 1 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bit cycles are same, then x should be hi - z. io 0 io 1 3 - byte address ... ... t v 22 20 18 7 5 3 1 7 5 3 1 7 5 3 1 4 dummy cy c les 23 21 19 ... 6 4 2 0 6 4 2 0 6 4 2 0 data out data out data out 16 14 12 17 15 13 10 11 sck 0 1 2 ... 6 7 8 9 10 11 12 13 14 15 16 mode 3 mode 0 ce # 7 5 3 1 6 4 2 0 0 1 mode bits ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 81 rev. a 09/02 /2016 8.41 fast read quad io dtr m ode operation in spi mode (frqdtr, ed h ) the frqdtr instruction enables double transfer rate throughput on quad i/o of the device in read mode. a qua d enable (qe) bit of status register must be set to "1" before sending the frqdtr instruction. the address (interleave on 4 i/o pins) is latched on both rising and falling edge of sck, and data (interleave on 4 i/o pins) shift out on both rising and fallin g edge o f sck at a maximum frequency f q2 . the 8 - bit address can be latched - in at one clock, and 8 - bit data can be read out at one clock, which means four bits at the rising edge of clock, the other four bits at the fall ing edge of clock. the first addres s byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out with a single frqdtr instruc tion. the address counter rolls over to 0 when the highest address is reached. once writing frqdtr instruc tion, the following address/dummy/data out will perform as 8 - bit instead of previous 1 - bit. the sequence of issuing frqdtr instruction is: ce# goes low ? s ending frqdtr instruction (1 - bit per clock) ? 24 - bit address interleave on io 3, io 2, io 1 & io 0 (8 - bit per clock) ? 6 dummy clocks (configurable , default is 6 clocks ) ? d ata out interleave on io 3, io 2, io 1 & io 0 (8 - bit per clock) ? e nd frqdtr operation by driving ce# hi gh at any time during data out. if axh ( where x is dont care ) is input for the mode bits during dummy cycles, the device will enter ax read operation mode which enables subsequent frqdtr execution skips command code. it saves cycles as described in figure 8. 6 8 . when the code is different from axh, the device exits the ax read operation. after finishing the read operation, device becomes ready to receive a new command. if the frqdtr instruction is issued while a program/erase/w rite status register cycle is in progress (wip=1), the instruction will be rejected without any effect on the current cycle.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 82 rev. a 09/02 /2016 figure 8.67 frqdtr sequence (with command decode cycles) notes: 1. if the mode bits=axh ( where x is dont care ), it can execute the ax read mode (without command) . when the mo de bits are different from axh , the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.1 1 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bit cycles are same, then x should be hi - z. ce # sck instruction = edh ce # sck 3 - byte address high impedance 0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 ... mode 3 mode 0 t v 20 16 12 5 1 21 17 13 data out 4 0 io 0 io 1 io 0 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 6 dummy cycles io 2 io 3 io 1 io 2 io 3 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 data out data out data out data out data out data out data out data out data out 13 5 1 4 0 6 2 7 3 mode bits ... ... ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 83 rev. a 09/02 /2016 figure 8.68 frqdtr sequence (without command decode cycles) notes: 1. if the mode bits=axh ( where x is dont ca re ), it will keep executing the ax read mode (without command) . when the mo de bits are different from axh , the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.1 1 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bit cycles are same, then x should be hi - z. ce # sck 3 - byte address 0 1 2 3 4 5 6 7 8 9 10 11 mode 3 mode 0 t v 20 16 12 5 1 21 17 13 4 0 io 0 io 1 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 6 dummy cycles io 2 io 3 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 5 1 4 0 6 2 7 3 data out data out data out data out 5 1 4 0 6 2 7 3 mode bits 12 ... ... ... ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 84 rev. a 09/02 /2016 fast read quad io dtr mode operation in qpi mode (frqdtr qpi, e dh) the frqdtr qpi instruction utilizes all fou r io lines to input the instruction code so that only two clocks are required, while the frqdtr instruction requires that the byte - long instruction code is shifted into the device only via io0 line in eight clocks. as a result, 6 command cycles will be reduced by the frqdtr qpi instruction. in addition, subsequent address and data out are shifted in/out via all four io lines like the frqdtr instruction. in fact, except for the command cycle, the frq dtr qpi operation is exactly same as the frqdtr . the sequence of issuing frqdtr qpi instruction is: ce# goes low ? sending frqdtr qpi instruction (4 - bit per clock) ? 24 - bit address interleave on io 3, io 2, io 1 & io 0 (8 - bit per clock) ? 6 dummy clocks (con figurable , default is 6 clocks ) ? data out interleave on io 3, io 2, io 1 & io 0 (8 - bit per clock) ? end frqdtr qpi operation by driving ce# high at any time during data out. if axh ( where x is dont care ) is input for the mode bits during dummy cycles, the device will enter ax read operation mode which enables subsequent fr qdtr qpi execution skips command code. it saves cycles as described in figure 8. 6 8 . when the code is different from axh, the device exits the ax read operation. after finishing the read op eration, device becomes ready to receive a new command. if the frqdtr qpi instruction is issued while a program/erase/write status register cycle is in progress (wip=1), the instruction will be rejected without any effect on the current cycle. figure 8.69 frqdtr qpi sequence (with command decode cycles) notes: 1. if the mode bits=axh ( where x is dont care ), it can execute the ax read mode (without command) . when the mo de bits are different from axh , the device exits the ax read operation. 2. number of dummy cycles depends on clock speed. detailed information in table 6.11 read dummy cycles. 3. sufficient dummy cycles are required to avoid i/o contention. if the number of dummy cycles and ax bit cycles are same, then x should be hi - z. instruction = edh ce # sck 3 - byte address 0 1 2 3 4 5 6 7 8 9 10 11 12 mode 3 mode 0 t v 20 16 12 5 1 21 17 13 4 0 io 0 io 1 22 18 14 23 19 15 8 4 0 9 5 1 10 6 2 11 7 3 6 dummy cycles io 2 io 3 6 2 7 3 5 1 4 0 6 2 7 3 data out data out 5 1 4 0 6 2 7 3 mode bits ... 4 0 5 1 6 2 7 3 ... ... ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 85 rev. a 09/02 /2016 8.42 sector l ock/unlock function s sector unlock operation (secunlock, 26h) the sector u nlock command allows the user to select a specific sector to allow program and erase operations. this instruction is effective when the blocks are designated as write - protected thro ugh the bp0, bp1, bp2 , and bp3 bits in the status register . only one sector can be enabled at any time. to enable a different sector, a previously enabled sector must be disabled by executing a sector lock command. the instruction code is followed by a 24 - bit address specifying the target sector, but a0 through a11 are not decoded. the remaining sectors within the same block remain as read - only. figure 8.70 s ec to r u n l o ck s e qu e n ce in spi m ode figure 8.71 s ec to r u n l o ck qpi s e qu e n ce in qpi m ode instruction = 26 h 23 ce # sck si 3 2 so 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0 26 h ce # sck io [ 3 : 0 ] 3 - byte address 0 1 2 3 4 5 6 7 mode 3 mode 0 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0 instruction
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 86 rev. a 09/02 /2016 sector lock operation (seclock, 24h) t he s e c tor lo c k c o mm and relocks a sector that was previously unlocked by the s e c tor u n l o c k c o m m a n d. t he i n s t r u c t i on c ode does n ot r e q u i r e an add r e s s to be s p e c i f i ed , as o n l y one s e c tor c a n b e e n a b l ed at a t i m e. t he r e m a i n i n g s e c to r s w i th i n t h e s a m e b l o c k r e m a i n i n r ead - o n l y m ode. figure 8.72 s e c to r lo c k se qu e n ce in spi m ode figure 8.73 s e c to r lo c k qpi se qu e n ce in qpi m ode instruction = 24 h ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance 24 h ce # sck io [ 3 : 0 ] 0 1 mode 3 mode 0
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 87 rev. a 09/02 /2016 8.43 autoboot spi devices normally require 32 or more cycles of command and address shifting to initiate a read command. and, in order to read boot code from an spi device, the host memory controller or processor must supply the read command from a hardwired state machine or from s ome host processor internal rom code. parallel nor devices need only an initial address, supplied in parallel in a single cycle, and initial access time to start reading boot code. the autoboot feature allows the host memory controller to take boot code fr om the device immediately after the end of reset, without having to send a read command. this saves 32 or more cycles and simplifies the logic needed to initiate the reading of boot code. ? as part of the power - up reset, hardware reset, or software reset process the autoboot feature automatically starts a read access from a pre - specified address. at the time the reset process is completed, the device is ready to deliver code from the starting address. the host memory controller only needs to drive ce# sign al from high to low and begin toggling the sck signal. the device will delay code output for a pre - specified number of clock cycles before code streams out. C the auto boot start delay (absd) field of the autoboot register specifies the initial delay if a ny is needed by the host. C the host cannot send commands during this time. C if qe bit (bit 6) in the status register is set to 1, fast read quad i/o operation will be selected and initial delay is the same as dummy cycles of fast read quad i/o read ope ration. if it is set to 0, fast read operation will be applied and initial delay is the same as dummy cycles of fast read operation. maximum operation frequency will be 133 mhz for both operations. ? the starting address of the boot code is selected by the value programmed into the autoboot start address (absa) field of the autoboot register. C data will continuously shift out until ce# returns high. ? at any point after the first data byte is transferred, when ce# returns high, the spi device will reset to standard spi mode; able to accept normal command operations. C a minimum of one byte must be transferred. C autoboot mode will not initiate again until another power cycle or a reset occurs. ? an autoboot enable bit (abe) is set to enable the autoboot fea ture. the autoboot register bits are non - volatile and provide: ? the starting address set by the autoboot start address (absa). ? the number of initial delay cycles, set by the autoboot start delay (absd) 4 - bit count value.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 88 rev. a 09/02 /2016 figure 8.74 autoboot sequence (qe = 0) figure 8.75 autoboot sequence (qe = 1) 7 ce # sck si 3 2 so 1 0 data out 1 high impedance 6 5 4 0 1 2 ... n - 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 mode 3 mode 0 t v absd delay ( n ) 7 6 ... data out 2 ... ... 4 ce # sck 4 0 4 0 high impedance 0 4 0 mode 3 mode 0 io 0 io 1 io 2 io 3 5 1 data out 1 5 1 5 1 5 1 7 3 6 2 7 3 7 3 6 2 6 2 7 3 6 2 data out 2 data out 3 data out 4 t v absd delay ( n ) 0 1 2 ... n - 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 ... 4 0 5 1 ... 7 3 ... 6 2 ... data out 5 ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 89 rev. a 09/02 /2016 autoboot register read operation (rdabr, 1 4 h) the autoboot regi ster read command is shifted in . then the 32 - bit autoboot register is shif ted out , least significant byte first, most significant bit of each byte first. it is possible to read the autoboot register continuously by providing multiples of 32 bits . figure 8.76 rdabr sequence in spi m ode figure 8.77 rdabr sequen ce in qpi m ode instruction = 14 h 7 ce # sck si 3 2 so 1 0 data out 1 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 t v ... ... 14 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] t v data out ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 90 rev. a 09/02 /2016 autoboot register write operation (wrabr, 1 5h) before the wrabr command can be accepted, a write enable (wren) command must be issued and d ecoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the wr abr command is entered by shifting the instruction and the data bytes , least significant byte first, most significant bit of each byte first. the wr abr data is 32 bits in length. ce # must be driven high after the 32 nd bit of data has been latched. if not, the wrabr command is not executed. as soon as ce # is driven high, the wrabr operation is initiated. while the wrabr operation is in progress, status register may be read to check the value of the write - in progress ( wip) bit. the wip bit is 1 during the wrabr operation, and is a 0 when it is completed. when the wrabr cycle is completed, the wel is set to 0 . figure 8.78 wrabr sequence in spi mode figure 8.79 wrabr sequence in qpi m ode instruction = 1 5 h 7 ce # sck si 3 2 so 1 0 data in 1 6 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 4 high impedance ... ... 15 h 0 1 mode 3 mode 0 2 3 7 : 4 3 : 0 ce # sck io [ 3 : 0 ] data in 1 ... ...
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 91 rev. a 09/02 /2016 9. electrical characteristics 9.1 absolute maximum rat ings (1) storage temperature - 6 5 c to +1 5 0 c surface mount lead soldering temperature standard package 240 c 3 seconds lead - free package 260 c 3 seconds input voltage with respect to ground on all pins - 0.5v to v cc + 0.5v all output voltage with respect to ground - 0.5v to v cc + 0.5v v cc is25lp - 0.5v to +6.0v is25wp - 0.5v to +2.5v electrostatic discharge voltage (human body model) (2) - 2000v to +2000v note s : 1. applied conditions greater than those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. ansi/esda/jedec js - 001 9.2 operating range operating temperature extended grade e - 4 0 c to 105 c extended+ grade e1 - 40c to 125c automotive grade a1 - 40c to 85c automotive grade a2 - 40c to 105c automotive grade a3 - 40c to 125c v cc power supply is25lp 2.3v (vmin) C 3.6v (vmax); 3. 0 v (typ) is25wp 1.65v (vmin) C 1.95v (vmax); 1.8v (typ)
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 92 rev. a 09/02 /2016 9.3 dc characteristics (under operating range) symbol parameter condition min typ (2) max units i cc1 v cc active read current (3) nord at 50 mhz, 4 6 ma frd single at 133 mhz 6 8 frd dual at 133 mhz 8 10 frd quad at 133 mhz 10 13 frd quad at 84 mhz 8 10 frd quad at 104 mhz 9 11 frd single d t r at 66 mhz 6 8 frd dual d t r at 66 mhz 8 10 frd quad d t r at 66 mhz 10 13 i cc2 v cc program current ce# = v cc 85 c 22 25 ma 105 c 25 125 c 25 i cc3 v cc wrsr current ce# = v cc 85 c 22 25 105 c 25 125 c 25 i cc4 v cc erase current (ser/ber32/ber64) ce# = v cc 85 c 22 25 105 c 25 125 c 25 i cc5 v cc erase current (ce) ce# = v cc 85 c 22 25 105 c 25 125 c 25 i sb1 v cc standby current cmos ce# = v cc 85 c 8 1 5 (4) a 105 c 20 (4) 125 c 30 i sb2 deep power down current is25lp ce# = v cc 85 c 6 10 (4) a 105 c 15 (4) 125 c 2 0 is25wp ce# = v cc 85 c 1 5 (4) 105 c 10 (4) 125 c 15 i li input leakage current v in = 0v to v cc 1 a i lo output leakage current v in = 0v to v cc 1 a v il (1) input low voltage - 0.5 0. 3 v cc v v ih (1) input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 100 a 0. 2 v v oh output high voltage i oh = - 100 a v cc - 0.2 v
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 93 rev. a 09/02 /2016 notes: 1. maximum dc voltage on input or i/o pins is vcc + 0.5v. during voltage transitions, input or i/o pins may overshoot vcc by + 2.0v for a period of time not to exceed 20ns. minimum dc voltage on input or i/o pins is - 0.5v. during voltage transitions, input o r i/o pins may undershoot gnd by - 2.0v for a period of time not to exceed 20ns. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), ta=25c . 3. outputs are unconnected during reading data so that output switching current is not included. 4. these parameters are characterized and are not 100% tested. 9.4 ac m easurement c onditions symbol parameter min max units cl load capacitance up to 104mhz 30 pf load capacitance up to 133mhz 15 pf tr,tf input rise and fall times 5 ns vin input pulse voltages 0.2v cc to 0.8v cc v vrefi input timing reference voltages 0.3v cc to 0.7v cc v vrefo output timing reference voltages 0.5v cc v figure 9. 1 output test load & ac measurement i/o waveform 9.5 pin capacitance (ta = 25c, vcc=3v (i s25lp x), 1.8v (is25wpx ), 1mhz) symbol parameter test condition min typ max units c in input capacitance (ce#, sck) v in = 0v - - 6 pf c in /out input/output capacitance (other pins) v in/o ut = 0v - - 8 pf notes: 1. these parameters are characterized and are not 100% tested. o u t p u t p i n 1 . 8 k 1 . 2 k 1 5 / 3 0 p f 0 . 8 v c c 0 . 2 v c c i n p u t v c c / 2 a c m e a s u r e m e n t l e v e l
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 94 rev. a 09/02 /2016 9.6 ac characteristics (under operating range, refer to section 9.4 for ac measurement conditions) symbol parameter min typ (3) max units f ct clock frequency for fast read mode: spi, dual, dual i/o, quad i/o, and qpi. 0 133 mhz f c2 , f t2 , f q2 clock frequency for fast read dtr: spi dtr, dual dtr, dual i/o dtr, quad i/o dtr, and qpi dtr. 0 66 mhz f c clock frequency for read mode spi 0 50 mhz t clch (1) sck rise time (peak to peak) 0.1 v/ns t chcl (1) sck fall time ( peak to peak) 0.1 v/ns t ckh sck high time for read mode 45% f c ns for others 45% f ct/c2/t2/q2 t ckl sck low time for read mode 45% f c ns for others 45% f ct/c2/t2/q2 t ceh ce# high time 7 ns t cs ce# setup time 5 ns t ch ce# hold time 5 ns t ds data in setup time normal mode 2 ns dtr mode 1.5 t dh data in hold time normal mode 2 ns dtr mode 1.5 t v output valid @ 133mhz (cl = 15pf) 7 ns @ 104mhz (cl = 30pf) 8 t oh output hold time 2 ns t dis (1) output disable time 8 ns t hlch hold active setup time relative to sck 2 ns t chhh hold active hold time relative to sck 2 ns t hhch hold not active setup time relative to sck 2 ns t chhl hold not active hold time relative to sck 2 ns t lz (1) hold to output low z 12 ns t hz (1) hold to output high z 12 ns t ec sector erase time (4kbyte) 70 300 ms block erase time (32kbyte) 0.1 0.5 s block erase time (64kbyte) 0.15 1.0 s chip erase time 2mb (4) 0.5 1.7 s 4mb (4) 1 3 8mb 2 6 t pp page program time 0. 2 0.8 ms
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 95 rev. a 09/02 /2016 symbol parameter min typ (3) max units t res1 (1) release deep power down is25lp 3 s is25wp 5 t dp (1) deep power down 3 s t w write status register time 2 15 ms t sus (1) suspend to read ready 100 s t srst (1) software reset recovery time 100 s t reset (1) reset# pin low pulse width 1 (2) s t hwrst (1) hardware reset recovery time 100 s notes: 1. these parameters are characterized and not 100% tested. 2. if the reset# pulse is driven for a period shorter than 1s ( t reset minimum ), it may still reset the device, however the 1s minimum period is recommended to ensure reliable operation. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), ta=25c . 4. 4mb/2mb are available only for 1.8v device.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 96 rev. a 09/02 /2016 9.7 serial input/output timing figure 9.2 serial input/output timing (normal mode) (1) note1 : for spi mode 0 (0,0) figure 9.3 serial input/output timing (dtr mode) (1) note1: for spi mode 0 (0,0) hi - z so si sck ce # valid in t cs t ckh t ckl t ds t dh t ch t ceh t v t dis hi - z t oh valid in valid output hi - z so si sck ce # valid in t cs t ckh t ckl t ds t dh t ch t ceh t v t dis hi - z t oh valid in valid in output output t v
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 97 rev. a 09/02 /2016 figure 9. 4 hold timing s i s o s c k c e # h o l d # t c h h l t h l c h t c h h h t h h c h t h z t l z
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 98 rev. a 09/02 /2016 9.8 power - up and power - down at power - up and power - down, the device must be not selected until vcc reaches at the right level. ( adding a simple pull - up resistor on ce# is recommended. ) power up timing symbol parameter min. max unit tvce (1) vcc(min) to ce# low 300 u s v wi (1) write inhibit voltage is25lp 2.1 v is25wp 1. 4 note: these parameters are characterized and not 100% tested. v cc v cc ( max ) v cc ( min ) v wi t vce device is fully accessible chip selection not allowed = vcc min . to ce # low time
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 99 rev. a 09/02 /2016 9.9 program/erase perfor mance parameter typ max unit sector erase time (4kbyte) 70 300 ms block erase time (32kbyte) 0.1 0.5 s block erase time (64kbyte) 0.15 1.0 s chip erase time 2mb 0.5 1.7 s 4mb 1 3 8mb 2 6 page programming time 0. 2 0.8 ms byte program 8 40 s note: these parameters are characterized and not 100% tested. 9.10 reliability characte ristics parameter min max unit test method endurance 1 00,000 - cycles jedec standard a117 data retention 20 - years jedec standard a117 latch - up - 100 +100 ma jedec standard 78 note: these parameters are characterized and not 100% tested.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 100 rev. a 09/02 /2016 10. p ackage type information 10.1 8 - pin jedec 208mil bro ad small outline int e grated circuit (soic ) package ( b) note: lead co - planarity is 0.1mm.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 101 rev. a 09/02 /2016 10.2 8 - pin jedec 150mil bro ad small outline int egrated cir cuit (soic) package ( n) note: lead co - planarity is 0.08mm.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 102 rev. a 09/02 /2016 10.3 8 - pin 150 mil v v sop package ( v ) note: lead co - planarity is 0.08mm.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 103 rev. a 09/02 /2016 10.4 8 - contact ultra - thin small outline no - lead (uson) package 2x3mm (u ) note: lead co - planarity is 0.08mm.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 104 rev. a 09/02 /2016 10.5 8 - contact ultra - thin small outline n o - lead (uson) package 4x3mm (t) note : lead co - planarity is 0.08mm.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 105 rev. a 09/02 /2016 10.6 8 - contact ultra - thin small outline no - lead (wson) package 6x5mm ( k) note: lead co - planarity is 0.08mm.
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 106 rev. a 09/02 /2016 11. ordering information - valid part numbers is 25lp 0 80 d - j b l e temperature range e = extended ( - 40 c to +105 c) e1 = extended+ ( - 40 c to +125 c) (call factory) a1 = automotive grade ( - 40 c to +85 c) a2 = automotive grade ( - 40 c to +105 c) a3 = automotive grade ( - 40 c to +125 c) packaging content l = rohs compliant package type ( 1 ) b = 8 - pin soic 208mil n = 8 - pin soic 150mil v = 8 - pin vvsop 150mil t = 8 - contact uson 4x3mm u = 8 - contact uson 2x3mm k = 8 - contact wson 6x5mm w = kgd (call factory) option j = standard die revision d = revision d density 080 = 8 megabit 040 = 4 megabit (call factory) 020 = 2 megabit (call factory) base part number i s = integrated silicon solution inc. 25lp = flash, 2.30 v ~ 3.60 v, qpi 25wp = flash, 1.65v ~ 1.95v, qpi note : 1 . call factory for other package options available
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 107 rev. a 09/02 /2016 density, voltage frequency (mhz) order part number (1) package 8mb, 3v str 133, dtr 66 is25lp080d - jble is25lp080 d - jble 1 (2) 8 - pin soic 208mil is25lp080d - jnle is25lp080 d - jnle 1 (2) 8 - pin soic 150mil is25lp080d - jvle is25lp080 d - jvle 1 (2) 8 - pin vvsop 150mil is25lp080d - jkle is25lp080 d - jkle 1 (2) 8 - contact wson 6x5mm is25lp080d - jtle is25lp080 d - jtle 1 (2) 8 - contact uson 4x3mm is25lp080d - jule is25lp080 d - jule 1 (2) 8 - contact uson 2x3mm is25lp080 d - jbla * ( 1 ) 8 - pin soic 208mil is25lp080 d - jnl a * ( 1 ) 8 - pin soic 150mil is25lp080 d - jvl a * ( 1 ) 8 - pin vvsop 150mil is25lp080 d - jkla * ( 1 ) 8 - c ontact wson 6x5mm is25lp080 d - jtla * ( 1 ) 8 - c ontact uson 4x3mm is25lp080 d - jula * ( 1 ) 8 - c ontact uson 2x3mm is25lp080 d - jwle (2) kgd
is25lp080 d is25wp080d /040d /020 d integrated silicon solution, inc. - www.issi.com 108 rev. a 09/02 /2016 note s : 1. a* = a1, a2, a3: meets aec - q100 requirements with ppap, e1= extended+ non - auto qualified temp grades: e= - 40 to 105 c, e1= - 40 to 125 c, a1= - 40 to 85 c, a2= - 40 to 105 c, a3= - 40 to 125 c 2. call fac tory density, voltage frequency (mhz) order part number package 8mb, 1.8v str 133, dtr 66 is25wp080 d - jble is25wp080 d - jble1 (2) 8 - pin soic 208mil is25wp080 d - jnle is25wp080 d - jnle1 (2) 8 - pin soic 150mil is25wp080 d - jvle is25wp080 d - jvle1 (2) 8 - pin vvsop 150mil is25wp080 d - jkle is25wp080 d - jkle1 (2) 8 - contact wson 6x5mm is25wp080 d - jtle is25wp080 d - jtle1 (2) 8 - contact uson 4x3mm is25wp080 d - jule is25wp080 d - jule1 (2) 8 - contact uson 2x3mm is25wp080 d - jbla * ( 1 ) 8 - pin soic 208mil is25wp080 d - jnla * ( 1 ) 8 - pin soic 150mil is25wp080 d - jvla * ( 1 ) 8 - pin vvsop 150mil is25wp080 d - jkla * ( 1 ) 8 - c ontact wson 6x5mm is25wp080 d - jtla * ( 1 ) 8 - c ontact uson 4x3mm is25wp080 d - jula * ( 1 ) 8 - c ontact uson 2x3mm is25wp080 d - jwle * (2) kgd 4mb, 1.8v str 133, dtr 66 is25wp040 d - jble (2) is25wp040 d - jble 1 (2) 8 - pin soic 208mil is25wp040 d - jnle (2) is25wp040 d - jnle 1 (2) 8 - pin soic 150mil is25wp040 d - jvle (2) is25wp040 d - jvle 1 (2) 8 - pin vvsop 150mil is25wp040 d - jkle (2) is25wp040 d - jkle 1 (2) 8 - contact wson 6x5mm is25wp040 d - jtle (2) is25wp040 d - jtle 1 (2) 8 - contact uson 4x3mm is25wp040 d - jule (2) is25wp040 d - jule 1 (2) 8 - contact uson 2x3mm is25wp040 d - jbla * ( 1, 2) 8 - pin soic 208mil is25wp040 d - jnla * ( 1, 2) 8 - pin soic 150mil is25wp040 d - jvla * ( 1, 2) 8 - pin vvsop 150mil is25wp040 d - jkla * ( 1, 2) 8 - c ontact wson 6x5mm is25wp040 d - jtla * ( 1, 2) 8 - c ontact uson 4x3mm is25wp040 d - jula * ( 1, 2) 8 - c ontact uson 2x3mm is25wp040 d - jwle (2) kgd 2mb, 1.8v str 133, dtr 66 is25wp020 d - jble (2) is25wp020 d - jble1 (2) 8 - pin soic 208mil is25wp020 d - jnle (2) is25wp020 d - jnle1 (2) 8 - pin soic 150mil is25wp020 d - jvle (2) is25wp020 d - jvle1 (2) 8 - pin vvsop 150mil is25wp020 d - jkle (2) is25wp020 d - jkle1 (2) 8 - contact wson 6x5mm is25wp020 d - jule (2) is25wp020 d - jule1 (2) 8 - contact uson 2x3mm is25wp020 d - jbla* ( 1, 2) 8 - pin soic 208mil is25wp020 d - jnla * ( 1, 2) 8 - pin soic 150mil is25wp020 d - jvla * ( 1, 2) 8 - pin vvsop 150mil is25wp020 d - jkla * ( 1, 2) 8 - c ontact wson 6x5mm is25wp020 d - jula * ( 1, 2) 8 - c ontact uson 2x3mm is25wp020 d - jwle * ( 2) k gd

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